參數(shù)資料
型號: DSP16210
英文描述: TVS 400W 6.5V UNIDIRECT SMA
中文描述: DSP16210數(shù)字信號處理器
文件頁數(shù): 81/173頁
文件大小: 2621K
代理商: DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
81
Software Architecture
(continued)
Instruction Set Quick Reference
(continued)
Table 35. F1 Instruction Syntax
Combine Any F1 Function Statement with Any Transfer Statement
F1 MAC Function Statement—
Combine Any Items in Following Two Columns:
ALU
Multiplier
aD =
aS
±
p0
p0 = xh * yh
(no ALU operation)
§
(no multiply operation)
§
F1 Arithmetic/Logic Function Statement (ALU)
aD =
aS OP
y
aS – y
aS & y
nop
(no F1 function statement)
§
Transfer Statement
Cycles
(Out/In
Cache)
1/1
1/1
1/1
1 + X
C
/1
1/1
Not including conflict, misalignment, or external wait-states (see the DSP16000 Digital Signal Processor Core nformation Manual).
This Y transfer statement must increment or decrement the contents of an
rM
register. It is not necessary to include the * before the
rM
reg-
ister because no access is made to a memory location.
Leave the ALU column blank to specify no ALU operation, the multiplier column blank to specify no multiply operation, or both columns
blank to specify no F1 function statement. If both columns are left blank and a transfer statement is used (a transfer-only F1 instruction,
i.e.,
yh = *r2 xh = *pt0++
), the assembler interprets the F1 function statement as a
nop
.
For this instruction,
a
must be the opposite of
aD
, e.g., if
aD
is
a0
,
a
must be
a1
and vice versa.
X
C
is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruction types and
can only be avoided by use of the cache. See the DSP16000 Digital Signal Processor Core nformation Manual.
§§ The assembler encodes an instruction that consists of a function statement
F1
with no transfer statement as
F1 *r0
.
nop
is no-operation. A programmer can write
nop
with or without an accompanying transfer statement. The assembler encodes
nop
with-
out a transfer statement as
nop *r0
.
16-Bit
Words
Y
h, l
= Y
D
1
§
x,
y, a
Y =
y, aT
h, l
yh =
Y, aTh
(no transfer)
§§
xh = X
D
D
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