Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
129
DSP16210 Boot Routines
(continued)
Commands
(continued)
Table 81. Command Encoding for Boot Routines
(continued)
0x29
0x2A
0x2B
0x2E
0x2F
0x32
0x34
0x35
0x36
0x37
0x69
0x6A
0x6B
0x6E
0x6F
0x72
0x74
0x75
0x76
0x77
0xA9
0xAA
0xAB
0xAE
0xAF
0xB2
0xB4
0xB5
0xB6
0xB7
0x0111
PHIF16
EROM
(64K)
16-bit
16-bit
Motorola
active-low
active-high
active-low
active-low
active-high
active-low
active-high
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-high
active-low
active-high
active-low
active-low
active-high
active-low
active-low
active-high
active-low
active-high
active-low
active-high
active-low
No
64 words
Intel
Motorola
Yes
1 word
Motorola
Yes
64 words
Motorola
No
512 words
Intel
Motorola
0x0222
No
64 words
Intel
Motorola
Yes
1 word
Motorola
Yes
64 words
Motorola
No
512 words
Intel
Motorola
0x0444
No
64 words
Intel
Motorola
Yes
1 word
Motorola
Yes
64 words
Motorola
No
512 words
Intel
Command
Code
mwait
Setting
Function/Download
Download
From
Download
To
Configuration
PHIF16
Mode
MIOU0
DMA
Block
External
Bus
Logical
Transfer
PODS/
PDS
Byte-
Swapping
The boot routine configures the PHIF16 by writing to the
PHIFC
register. Specifically, the external bus configuration, logical transfer size, and
byte swapping are controlled by the PMODE and PCFIG fields, the mode is controlled by the PSTROBE field, and the PODS/PDS active-
low/high configuration is controlled by the PSTRB field. After the download is complete, the boot routine returns the PHIF16 to its initial state
(configures it for Intelmode with an 8-bit external bus and 8-bit logical transfers).
This is the size of each input DMA transfer that the boot routine directs the MIOU0 to perform without core intervention. MIOU0 performs
input DMA from the PHIF16 block. The boot routine configures the input block size by programming the
ILEN0
register.
§ The first 60 Kword locations of the segment are copied into the DPRAM.