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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 42/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
42
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Modular I/O Units (MIOUs)
The DSP16210 contains two identical modular I/O
units: MIOU0 (provides DMA for the PHIF16) and
MIOU1 (provides DMA for the SSIO).
An MIOU provides programmable DMA capability.
Figure 16
shows the MIOUs, their connections to the
IORAMs, the attached I/O peripherals, and the IDB.
Each MIOU interfaces its attached peripheral to a sin-
gle 1 Kword bank of IORAM storage that resides in the
DSP16000 core’s Y-memory space. Input and output
buffers for each peripheral are allocated in each
IORAM.
Figure 16. Modular I/O Units
IORAM
IORAM storage consists of two 1 Kword banks of mem-
ory, IORAM0 and IORAM1. Each IORAM bank has two
16-bit data and two 10-bit address ports. An IORAM
bank can be shared by the core and an MIOU to imple-
ment a DMA-based I/O system. IORAM supports con-
current core execution and MIOU I/O processing.
Portions of IORAM not dedicated to I/O processing can
be used as general-purpose data storage. However, a
high collision rate between core and MIOU accesses to
IORAM impacts core and I/O performance.
The IORAMs reside in the core’s Y-memory space (see
Figure 6 on page 26
). The EMI interfaces the core to
the IORAMs by translating between YAB/YDB
accesses and EAB/EDB accesses. This translation is
functionally transparent to the programmer. The core
can access the IORAM as single words or as double
words and the EMI automatically performs the required
multiplexing and sequencing. Core accesses to IORAM
cause the core to incur wait-states (see
External Mem-
ory Interface (EMI) beginning on page 27
). If the core
and an MIOU simultaneously access the same IORAM,
the MIOU access occurs first followed by the core
access and the core incurs a conflict wait-state.
MIOU Registers
For each MIOU, software controls DMA operations by
programming three registers that are directly program-
accessible:
mcmd
0,1
,
miwp
0,1
, and
morp
0,1
.
See
Table 16 on page 43
for a description of these reg-
isters.
In the DSP16000 instruction set,
mcmd
0,1
,
miwp
0,1
, and
morp
0,1
are off-core registers in the
RAB and RB register sets.
Table 15
summarizes the
instructions for programming these registers.
Table 17 on page 43
summarizes the MIOU registers
that are accessible by executing an MIOU command.
Software executes an MIOU command by writing to
mcmd
0,1
. See
MIOU Commands beginning on
page 43
for more information.
Table 15. Instructions for Programming MIOU Registers
DSP16000 CORE
XAB
YDB
EMI
MIOU0
mcmd0
PHIF16
XDB
YAB
IDB
EDB
EAB
IDB
data
address
IORAM0
1K
morp0
miwp0
16
10
MIOU1
mcmd1
SSIO
data
address
IORAM1
1K
32
32
20
32
20
data
address
data
address
16
10
16
10
10
16
16
10
morp1
miwp1
Instruction Syntax
RAB = IM20
RB = aTE
h, l
aTE
h, l
= RB
Substitution
Example
RAB
RB
mcmd
0,1
,
miwp
0,1
, or
morp
0,1
mcmd
0,1
,
miwp
0,1
, or
morp
0,1
mcmd0 = 0x6000
miwp1 = a3h
a0l = morp0
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