- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377000 > DSP16210 TVS 400W 6.5V UNIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 27/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
27
Hardware Architecture
(continued)
Memory Maps
(continued)
The addresses shown in Figures
5
and
6
correspond to
the 20-bit core address buses (XAB for the XMAP and
YAB for YMAP0/YMAP1). For external memory
accesses, these 20-bit addresses are truncated to
16 bits and the external enable pins (EROM, ERAMHI,
ERAMLO, and IO) differentiate the 64K segment being
accessed. For IORAM accesses, these 20-bit
addresses are truncated to 10 bits.
Boot from External ROM
The EXM pin determines from which memory region
(EROM or IROM) the DSP16210 executes code follow-
ing a device reset. EXM is captured by the rising edge
of RSTB. If the captured value of EXM is one, the
DSP16210 boots from external ROM (EROM—core
address 0x80000). Otherwise, the DSP16210 boots
from internal IROM (core address 0x20000). See
DSP16210 Boot Routines beginning on page 126
for
details on booting from IROM.
Data Memory Map Selection
The DSP16210 data memory map selection is based
on the value of the WEROM field (bit 4) in the
ioc
regis-
ter (
Table 54 on page 99
). If WEROM is set to 0, the
YMAP0 data memory map is selected. If WEROM is
set to 1, the YMAP1 data memory map is selected. If
WEROM is 1, all ERAMLO accesses are redirected to
the EROM segment.
External Memory Interface (EMI)
The external memory interface (EMI) manages off-chip
memory and on-chip IORAM memory and ESIO stor-
age, collectively referred to as EMI storage.
The EMI multiplexes the two sets of core buses
(XAB/XDB and YAB/YDB) onto a single set of external
buses—a 16-bit address bus (AB) and 16-bit data bus
(DB). It also multiplexes the two sets of core buses
onto a single set of internal EMI buses—a 10-bit
address bus (EAB) and a 16-bit data bus (EDB)—for
access to the IORAM and ESIO storage. The EMI auto-
matically translates 32-bit XDB/YDB accesses into two
16-bit DB/EDB accesses and vice versa. If an instruc-
tion accesses EMI storage from both the X side and Y
side, the EMI performs the X access first followed by
the Y access and the core incurs a conflict wait-state.
The EMI accesses four external memory segments—
ERAMHI, ERAMLO, EROM, and IO.
Two control registers are encoded by the user to define
the operation of the EMI. Bits 14—0 in
mwait
(
Table 58 on page 101
) and bits 10 and 7—0 in
ioc
(
Table 54 on page 99
) apply to the EMI. These pro-
grammable features give the designer flexibility in
choosing among various external memories.
Latency for Programming mwait and ioc Registers
There is a two instruction cycle latency between an
instruction that updates either
ioc
or
mwait
and avail-
ability of the new value in the EMI. It is recommended
that two
nop
s (or other instructions that do not access
external memory) follow each
ioc
or
mwait
update
instruction. See the example below:
mwait=0x0222/* Modify mwait
2*nop
/* Wait for latency
a0=*r0
/* OK to perform EMI read */
*/
*/
For write operations the EMI buffers the data (see
Functional Timing beginning on page 29
), software
must verify that all pending external write operations
have completed before modifying
ioc
or
mwait
. Software ensures that all memory operations
have completed by executing an external memory read
operation. After the read operation is completed, it is
safe to modify
ioc
or
mwait
. See the code segment
below for an example:
*r1++=a1
a0=*r2
mwait=0x0222/* Safe to modify mwait.
2*nop
/* Wait for mwait latency. */
/* EMI write.
/* Dummy EMI read.
*/
*/
*/
Note:
For the EMI to function properly, the application
program
must
adhere to the latency restrictions
presented above.
相關PDF資料 |
PDF描述 |
|---|---|
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
| DSP16410 | 16-bit fixed point DSP with Flash |
| DSP25-16AR | Phase-leg Rectifier Diode |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSP1627 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1627 Digital Signal Processor |
| DSP1627F32K10IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| DSP1627F32K11IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
發(fā)布緊急采購，3分鐘左右您將得到回復。