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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 35/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
35
Hardware Architecture
(continued)
Enhanced Serial I/O Unit (ESIO)
(continued)
Frame Input Mode Processing.
The ESIO operates in
frame input mode (IMODE) when (bit 8) of the
ICR
reg-
ister is cleared. (IMODE is cleared on reset.) The ESIO
demultiplexes multiple channels from a serial stream
consisting of a frame of 64, 128, 192, or 256 bits. The
input frame size (IFRMSZ) is specified by (bits [11:10])
of the
ICR
register. The start of a new frame is signaled
by the rising edge of the input frame sync (IFS). The
ESIO ignores input until it has detected the beginning
of a valid frame. Serial data is captured by the falling
edge of the input bit clock (IBC) (see
Figure 9 on
page 33
).
See
Figure 10 on page 34
for a diagram of the
IDMX
structure. The input section contains 16 double-buff-
ered 16-bit serial-to-parallel input demultiplexers with
provision for either 8-bit (ISIZE = 1) or 16-bit (ISIZE =
0) right-justified data. Each logical channel has a dedi-
cated 16-bit shift register that receives demultiplexed
serial data and has a dedicated 16-bit parallel read reg-
ister (
IDMX
0—15
). Each shift register is clocked indi-
vidually by IBCQ[15:0], a qualified IBC bit clock that
starts when the internal bit counter matches the input
logical channel start bit specified by the corresponding
ICSB
0—7
register (see
Table 11
).
Table 11. Input Channel Start Bit Registers
The clock IBCQ[15:0] is asserted in each frame for the
number of cycles that matches the programmed sam-
ple length for the corresponding logical channel. The
sample length is specified by one of the
ICSL
0—1
registers (see
Table 49 on page 96
).
Figure 11 is a timing diagram that depicts the clock
IBCQ3 assuming that the sample length is 2 bits
(
ICSL0
[7:6] = 01) and the start bit is 63
(
ICSB1
[15:8] = 0x3F). In this example, bits B
63
and B
64
are clocked into the shift register for logical channel 3.
When 16 serial input bits have been captured for a
given channel n the ESIO asserts IDLDn(see
Figure 10 on page 34
), transferring the shift register
contents to the channel’s parallel read register,
IDMXn
.
This transfer occurs every 2, 4, 8, or 16 frames
depending on the sample length programmed for chan-
nel n via
ICSL
0—1
. This serial-to-parallel transfer
permits a 16-bit word of channel data to be captured (at
the IBC rate) while the previous word is read by the
core.
Figure 11. Serial Input Clocking Example
The ESIO is programmed to generate the input buffer
full (EIBF) interrupt and assert the EIBF output pin at
the completion of every 2, 4, 8, or 16 frames depending
on the IFIR field of the
ICR
register (
Table 47 on
page 95
). EIBF is cleared if the DSP program reads
any of the
IDMX
0—15
registers or if it resets the input
section (writes
ICR
with the IRESET field (bit 4) set).
EIBF is first asserted when the programmed number of
input frames have been received following initialization
of the ESIO input section. The programmer initializes
the input section by simultaneously resetting it and
enabling it, i.e., by writing
ICR
with the IRESET field set
and the ICA field (bit 2) set. The IRESET field clears
itself automatically every cycle of the internal clock
(CLK). Therefore, when
ICR
is read, the value of the
IRESET field is always clear.
15
—
8
7
—
0
ICSB0
ICSB1
ICSB2
ICSB3
ICSB4
ICSB5
ICSB6
ICSB7
Channel 1
Channel 3
Channel 5
Channel 7
Channel 9
Channel 11
Channel 13
Channel 15
Channel 0
Channel 2
Channel 4
Channel 6
Channel 8
Channel 10
Channel 12
Channel 14
Field
Channel 0
to
Channel
15
Value
0x00
to
0xFF
Description
Start bit position for corresponding
logical input channel.
Ranges from 0 to 255.
IBC
EDI
B
63
B
62
B
64
B
65
IBCQ3
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