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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 53/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
53
Hardware Architecture
(continued)
Bit Input/Output Unit (BIO)
(continued)
Two instruction cycles of latency are required following
a BIO
cbit
register write operation before the new BIO
flags are available:
cbit= 0x0302
2*nop /* nops or other instructions */
if allt goto OK/* New Flags are visible*/
Pin Multiplexing
Four of the eight BIO signals (IOBIT[7:4]) are multi-
plexed with the four vectored interrupt ID signals
(VEC[3:0]) onto four package pins. Upon reset,
VEC[3:0] are connected to the pins while IOBIT[7:4]
are disconnected. Setting bit 8, EBIO, of the
ioc
regis-
ter connects IOBIT[7:4] to the pins and disconnects
VEC[3:0]. Note that VEC0 corresponds to IOBIT7,
VEC1 corresponds to IOBIT6, VEC2 corresponds to
IOBIT5, and VEC3 corresponds to IOBIT4.
Timers
The DSP16210 contains two identical independent tim-
ers, TIMER0 and TIMER1. TIMER
0,1
interrupts the
core after a programmed delay or repetitively at a pro-
grammed interval.
Each timer contains a 16-bit control register
(
timer
0,1
c
), down counter, period register, and a
4-bit prescaler. The 16-bit
timer
0,1
running count
register corresponds to the down counter and period
register. If
timer
0,1
is read, it returns the output of
the down counter. If
timer
0,1
is written, the write
value is loaded into the down counter and the period
register simultaneously. The prescaler divides the
internal clock (CLK) by a programmed value in the
range 2 to 65536. The down counter decrements every
cycle of the prescaled clock. When it reaches zero, the
timer asserts its interrupt (TIME
0,1
). The interrupt
delay is a function of the CLK frequency, the initial
value programmed in
timer
0,1
, and the prescale
value. For periodic timed interrupts, the timer can be
programmed to repetitively reload the down counter
with the contents of the period register.
See
Table 71
and
Table 72 on page 111
for descrip-
tions of
timer
0,1
and
timer
0,1
c
.
By default after reset, the timers are powered up and
the down counter holds its current count. To save
power if the timer is not in use, set the PWR_DWN bit
of
timer
0,1
c
. Setting
powerc
[TIMER
0,1
] (see
Table 65 on page 106
) has the same effect as setting
that timer’s PWR_DWN bit.
Assuming the timer is powered up, setting the COUNT
bit of
timer
0, 1
c
enables the clock to the down
counter. Clearing COUNT causes the counter to hold
its current value.
The PRESCALE[3:0] field of
timer
0,1
c
selects one of
16 possible clock rates for the input clock to the down
counter (see
Table 72 on page 111
). The clock rate is
the frequency of CLK divided by 2
N + 1
, where N is
PRESCALE[3:0] and ranges from 0 to 15.
To operate the timer, the software writes a value to
timer
0,1
and sets the COUNT bit of
timer
0,1
c
(the
remaining fields of
timer
0,1
c
must also be pro-
grammed appropriately). This causes the down counter
to start decrementing. When the counter reaches zero,
a vectored interrupt to program address
vbase
+ offset
1
is issued, providing the appropriate
timer interrupt is enabled
2
and no higher priority inter-
rupt is pending or being serviced. If the RELOAD bit of
timer
0,1
c
is 0, the timer stops decrementing the
counter when it reaches zero. Software can restart the
timer by writing a nonzero value to
timer
0,1
. If
RELOAD is 1, the timer reloads the counter from the
period register and the counter resumes decrementing,
resulting in repetitive periodic interrupts.
Software can start and stop the timer at any time
3
by
setting and clearing the COUNT bit. Software can read
and write
timer
0,1
at any time
3
. Due to pipeline
stages, stopping and starting the timers can result in an
error at one count or prescaled period.
When the DSP16210 is reset, the
timer
0,1
c
and
timer
0,1
registers and counters are cleared. This
powers up the timer, sets the prescale value to CLK/2,
disables the clock to the down counter, and turns off
the reload feature. The act of resetting the chip does
not cause a timer interrupt.
Note:
The timer must be powered up (PWR_DWN = 0
and
powerc
[1,0] = 0) in order to read or write the
timer
0,1
register. If
timer
0,1
is read after
device reset without first being written, a value of
all zeros is returned. However, the initial count
value and period are not cleared on reset—to
clear them, the software must write
timer
0,1
with all zeros.
1. offset is 0x34 for TIMER0 and 0x38 for TIMER1.
2. The programmer enables the TIMER0 interrupt by setting
inc0
bits 18 and 19 to a priority. The programmer enables the TIMER1
interrupt by setting
inc1
bits 0 and 1 to a priority. See
Table 52 on
page 97
for details.
3. The timer must be powered up.
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