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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 56/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
56
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Clock Synthesis
The DSP16210 provides an on-chip programmable clock synthesizer that can be driven by an external clock at a
fraction of the desired instruction rate.
Figure 18
is the synthesizer block diagram, which is based on a phase-lock
loop (PLL). The terms clock synthesizer and PLL are used interchangeably.
Notes:
If PLLEN is set, the PLL is enabled (powered up). If PLLEN is cleared, the PLL is disabled (powered down).
The PLL sets the LOCK flag when its output is stable. The LOCK flag is an input to CORE0 and to CORE1.
Figure 18. Clock Synthesizer (PLL) Block Diagram
Figure 19 on page 57
illustrates the internal clock
selection and disable logic. The clock selection logic
selects the internal clock (CLK) from one of the follow-
ing three clock sources:
I
CKI: This pin is driven by an external oscillator or the
pin’s associated boundary-scan logic under JTAG
control. If CKI is selected as the clock source, then
CLK has the frequency and duty cycle of CKI.
I
PLL: The PLL generates a clock source with a pro-
grammable frequency (an M/2N multiple of the CKI
clock). The PLLs output is f
PLL
. If the PLL is selected
as the clock source, then CLK has the frequency and
duty cycle of the PLL output f
PLL
.
I
Ring Oscillator: The internal ring oscillator produces
a slow clock that requires no external
stimulus. When the slow clock is selected as the
clock source, then CLK has the frequency and duty
cycle of the ring oscillator output. The core con-
sumes less power when clocked with the slow
clock. See
Table 91 on page 141
for timing charac-
teristics of the ring oscillator.
After device reset, CKI is selected as the default clock
source for the DSP16210. Setting the appropriate bits
in the
pllc
and
powerc
control registers (
Table 64 on
page 105
and
Table 65 on page 106
) enables either the
PLL or the ring oscillator to become the clock source.
Table 28
defines the selection of the three clock
sources as a function of the PLLSEL field (bit 14 of
pllc
) and the SLOWCLK field (bit 10 of
powerc
).
Table 28. Clock Source Selection
PLLSEL
(pllc[14])
(powerc[10])
0
0
1
The clock disable logic provides several methods for
shutting off the internal clock to save power. See
Power Management beginning on page 61
for details.
LOCK
PLL
f
CKI
Nbits[2:0]
(pllc[7:5])
Mbits[4:0]
(pllc[4:0])
LF[3:0]
(pllc[11:8])
÷
M
÷
N
PHASE
DETECTOR
LOOP
FILTER
CHARGE
PUMP
VCO
CKI
f
PLL
PLLEN
(pllc[15])
÷
2
SLOWCLK
f
CLK
Description
0
1
X
f
CKI
CKI pin
f
SLOW CLOCK
Ring Oscillator
f
PLL
PLL
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