參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 70/173頁
文件大小： 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
70
DRAFT COPY
Lucent Technologies Inc.
Software Architecture
(continued)
Instruction Set Quick Reference
(continued)
See the DSP16000 Digital Signal Processor Core nformation Manual and DSP16000 Digital Signal Processor
Core Instruction Set Reference Manual for a detailed description of:
I
The Instruction Set
I
Pipeline Hazards
1
I
Instruction Encoding Formats and Field Descriptions
I
Instruction Set Reference
Table 32 starting on page 71
lists the entire instruction set with its cycle performance and the number of instruc-
tion/coefficient memory locations required for each. Below is an illustration of a single row of the table and a
description of how to interpret its contents.
Figure 22. Interpretation of the Instruction Set Summary Table
Table 33 on page 77
summarizes the instruction set notation conventions for interpreting the instruction syntax
descriptions.
Table 34 starting on page 78
is an overall replacement table that summarizes the replacement for
every upper-case character string in the instruction set summary table (
Table 32
) except for F1 and F1E in the MAC
instruction group.
Table 35 on page 81
describes the replacement for the F1 field and
Table 36 starting on page 83
describes the replacement for the F1E field.
1. A pipeline hazard occurs when a write to a register precedes an access that uses the same register and that register is not updated because
of pipeline timing. The DSP16000 assembler automatically inserts a
nop
in this case to avoid the hazard.
Instruction
Flags
szlme
Cycles
Out
Words
In
ALU Group
aD = aS OP
aTE,pE
(F3)
szlm–
1
1
1
INSTRUCTION SYNTAX
INSTRUCTIONS ARE GROUPED INTO
CATEGORIES (ONE OF SEVEN).
QUANTITY OF PROGRAM MEMORY
USED BY THE INSTRUCTION.
(EITHER 1 OR 2 16-bit words)
F TITLE
(IF APPLICABLE)
THE NUMBER OF INSTRUCTION CYCLES
USED WHEN THE INSTRUCTION IS EXE-
CUTED OUTSIDE OF THE CACHE.
THE NUMBER OF INSTRUCTION CYCLES
USED WHEN THE INSTRUCTION IS EXE-
CUTED INSIDE OF THE CACHE
.
A DASH
(—) INDICATES THE INSTRUCTION IS NOT
CACHABLE.
FLAGS AFFECTED BY
THIS INSTRUCTION
szlme corresponds to the LMI (s), LEQ (z), LLV (l), LMV (m), and EPAR (e) flags
.
If a letter appears in this column, the corresponding flag is
affected by this instruction
.
If a dash appears in this column, the corresponding flag is unaffected by this instruction
.
In the example shown,
the instruction affects all flags except for EPAR
.
For MAC group instructions with both an ALU/ACS operation and an ADDER or BMU oper-
ation, the ALU/ACS result affects the LMI, LEQ, LLV, and LMV flags and the EPAR flag is unaffected. See Table 37 on page 85 for additional
information.
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