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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 24/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
24
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Interrupts and Trap
(continued)
INT[3:0] and TRAP Pins
The DSP16210 provides four interrupt pins INT[3:0].
TRAP is a bidirectional pin. At reset TRAP is config-
ured as an input to the processor. Asserting the TRAP
pin forces a pin trap. The trap mechanism is used to
rapidly gain control of the processor for asynchronous
time-critical event handling (typically for catastrophic
error recovery). A separate vector, PTRAP is provided
for the pin trap (see
Table 4 on page 21
). Traps cannot
be disabled.
Referring to the timing diagram in
Figure 3
, the INT[3:0]
or TRAP pin is asserted for a minimum of two cycles.
The pin is synchronized and latched on the next falling
edge of CLK. A minimum of four cycles later, the inter-
rupt or trap gains control of the core and the core
branches to the interrupt service routine (ISR) or trap
service routine (TSR). The actual number of cycles
until the interrupt or trap gains control of the core
depends on the number of wait-states incurred by the
interrupted or trapped instruction. The DSP16210
drives a value (see
Table 4 on page 21
) onto the
VEC[3:0] pins and asserts the IACK pin.
Low-Power Standby Mode
The DSP16210 has a power-saving standby mode in
which the internal core clock stretches indefinitely until
the core receives an interrupt or trap request. A mini-
mum amount of core circuitry remains active in order to
process the incoming interrupt. The clocks to the
peripherals are unaffected and the peripherals con-
tinue to operate during standby mode. The program
places the core in standby mode by setting the AWAIT
bit (bit 15) of the
alf
register (
alf
= 0x8000). After the
AWAIT bit is set, one additional instruction is executed
before the standby mode is entered. When an interrupt
occurs, core hardware resets AWAIT, and normal core
processing is resumed.
The MIOUs remain operational even in standby mode.
Their clocks remain running and they continue any
DMA activity.
Two
nop
instructions should be programmed after the
AWAIT bit is set. The first
nop
(one cycle) is executed
before sleeping; the second is executed after the inter-
rupt signal awakens the DSP and before the interrupt
service routine is executed.
Power consumption can be further reduced by activat-
ing other available low-power modes. See
Power Man-
agement beginning on page 61
for information on
these other modes.
Figure 3. INT[3:0] and TRAP Timing
CKO
IACK
VEC[3:0]
A
B
C
INT[3:0]/TRAP
CKO is programmed to be CLK.
The INT[3:0] or TRAP pin must be held high for a minimum of two cycles.
Notes:
A. The DSP16210 synchronizes and latches the INT[3:0] or TRAP
B. A minimum four-cycle delay before the core services the interrupt or trap (executes instructions starting at the vector location). For a trap, the
core executes a maximum of three instructions before it services the trap.
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