參數(shù)資料
型號(hào)： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號(hào)處理器
文件頁數(shù)： 96/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
96
DRAFT COPY
Lucent Technologies Inc.
Software Architecture
(continued)
Registers
(continued)
Register Settings
(continued)
Table 48. ICSB
0—7
(ESIO Input Channel Start Bit) Registers
Note:
These registers are not directly program-accessible (memory-mapped to addresses 0xE0010—0xE0017).
Table 49. ICSL
0—1
(ESIO Input Channel Sample Length) Registers
Note:
These registers are used only in frame mode (
ICR
[IMODE] = 0) and are not directly program-accessible
(memory-mapped to addresses 0xE0018—0xE0019).
Table 50. ICVV (ESIO Input Channel Valid Vector) Register
Note:
This register is not directly program-accessible (memory-mapped to address 0xE001B). For simple mode,
enable only logical channel 0, i.e., set
ICVV
to 0x0001. For frame mode, the bits in
ICVV
must be packed,
i.e., channels must be allocated from 0 to 15 with no holes between valid channels. For example, if
ICVV
contains 0x00FF, then logical channels 0—7 are enabled and demultiplexed. A value of 0x08FF for
ICVV
is
invalid because the channels are not packed.
15
14
13
12
Channel 15
Channel 14
Channel 13
Channel 12
7
6
5
4
Channel 7
Channel 6
Channel 5
Channel 4
15
—
8
7
—
0
ICSB0
ICSB1
ICSB2
ICSB3
ICSB4
ICSB5
ICSB6
ICSB7
Channel 1
Channel 3
Channel 5
Channel 7
Channel 9
Channel 11
Channel 13
Channel 15
Channel 0
Channel 2
Channel 4
Channel 6
Channel 8
Channel 10
Channel 12
Channel 14
Field
Channel 0
to
Channel 15
Value
0x00
to
0xFF
Description
Start bit position for corresponding logical input channel. Ranges from 0 to 255.
15
—
14
Channel 7
13
—
12
Channel 6
11
—
10
Channel 5
9
—
8
7
—
6
5
—
4
3
—
2
1
—
0
ICSL0
ICSL1
Channel 15 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10
Channel 4
Channel 3
Channel 2
Channel 1
Channel 9
Channel 0
Channel 8
Field
Channel 0
to
Channel 15
Value
00
01
10
11
Description
Input sample length is 1 bit (serial-to-parallel transfer rate is every 16 frames).
Input sample length is 2 bits (serial-to-parallel transfer rate is every 8 frames).
Input sample length is 4 bits (serial-to-parallel transfer rate is every 4 frames).
Input sample length is 8 bits (serial-to-parallel transfer rate is every 2 frames).
11
10
9
8
Channel 11
3
Channel 3
Channel 10
2
Channel 2
Channel 9 Channel 8
1
Channel 1 Channel 0
0
Field
Channel 0
to
Channel 15
Value
0
Description
Disable the corresponding logical input channel, i.e., do not demultiplex the input data
stream for this logical channel.
Enable the corresponding logical input channel, i.e., demultiplex the input data stream for
this logical channel.
1
相關(guān)PDF資料
PDF描述
DSP1627 TVS 400W 6.5V BIDIRECT SMA
DSP1629 TVS 400W 64V UNIDIRECT SMA
DSP16410C TVS 400W 7.0V UNIDIRECT SMA
DSP16410 16-bit fixed point DSP with Flash
DSP25-16AR Phase-leg Rectifier Diode
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP1627 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1627 Digital Signal Processor
DSP1627F32K10IR 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC
DSP1627F32K10IT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC
DSP1627F32K11I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor
DSP1627F32K11IR 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*