TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers
(continued)
118
Agere Systems Inc.
Table 123. TMUX_B3SF_CTL[1
—
6], B3 Signal Fail Set/Clear Control Registers (R/W)
Table 124. TMUX_B1ECNT, Receive B1 Error Counts (RO)
0x4005E
14:7
TMUX_B3SDMCLEAR[7:0]
B3 Signal Degrade M Clear.
Threshold of the
number of bad monitoring blocks in an observation
interval. If the number of bad blocks is below this
threshold, then SD is cleared.
B3 Signal Degrade L Clear.
Error threshold for
determining if a monitoring block is bad.
B3 Signal Degrade B Clear.
Number of monitoring
blocks.
0x00
6:3
TMUX_B3SDLCLEAR[3:0]
0x0
0x4005F
15:0
TMUX_B3SDBCLEAR[15:0]
0x0000
Address
Bit
Name
Function
Reset
Default
0x0000
0
0x00
0x40060
0x40061
0x40061
15:0
2:0
14:7
TMUX_B3SFNSSET[18:3]
TMUX_B3SFNSSET[2:0]
B3 Signal Fail Ns Set.
Number of frames in a
monitoring block for SF.
B3 Signal Fail M Set.
Threshold of the number of
bad monitoring blocks in an observation interval. If
the number of bad blocks is above this threshold,
then SF is set.
B3 Signal Fail L Set.
Error threshold for
determining if a monitoring block is bad.
B3 Signal Fail B Set.
Number of monitoring blocks. 0x0000
B3 Signal Fail Ns Clear.
Number of frames in a
monitoring block for SF.
B3 Signal Fail M Clear.
Threshold of the number of
bad monitoring blocks in an observation interval. If
the number of bad blocks is below this threshold,
then SF is cleared.
B3 Signal Fail L Clear.
Error threshold for
determining if a monitoring block is bad.
B3 Signal Fail B Clear.
Number of monitoring
blocks.
TMUX_B3SFMSET[7:0]
0x40061
6:3
TMUX_B3SFLSET[3:0]
0x0
0x40062
0x40063
0x40064
0x40064
15:0
15:0
2:0
14:7
TMUX_B3SFBSET[15:0]
TMUX_B3SFNSCLEAR[18:3]
TMUX_B3SFNSCLEAR[2:0]
0x0000
0
0x00
TMUX_B3SFMCLEAR[7:0]
0x40064
6:3
TMUX_B3SFLCLEAR[3:0]
0x0
0x40065
15:0
TMUX_B3SFBCLEAR[15:0]
0x0000
Address
Bit
Name
Function
Reset
Default
0x0000
0x40066
15:0
TMUX_B1ECNT[15:0]
Receive High-speed B1 Error Count.
Counts the number
of B1 errors in the received STS-3/STM-1 (AU-4) frame.
This counter can either count actual BIP errors or block
errors; see TMUX_BITBLKB1 (
Table 95
). This counter
holds at its maximum value or rolls over depending on the
value of SMPR_SAT_ROLLOVER (
Table 67
) and transfers
its internal count to a holding register when
SMPR_PMRESET (
Table 65
) transitions from a logic 0 to 1.
Table 122. TMUX_B3SD_CTL[1
—
6], B3 Signal Degrade Set/Clear Control Registers (R/W)
(continued)
Address
Bit
Name
Function
Reset
Default