TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
438
Agere Systems Inc.
19 VT/TU Mapper Functional Description
(continued)
VT/TU mapper automatic AIS, which is driven over a 28-bit internal output bus to the cross connect (XC), is gener-
ated according to the following equation:
SPEMPR_AUTO_AIS
or
VT_LOP[1
—
28]
or
VT_AIS[1
—
28]
or
(VT_H4LOMF and (VT_LOMF_AIS_INH))
or
(VT_UNEQ[1
—
28] and (VT_UNEQ_AIS_INH))
or
(VT_PLM[1
—
28] and (VT_PLM_AIS_INH))
or
(VT_J2TIM[1
—
28] and (VT_J2TIM_AIS_INH))
or
(VT_LOPS[1
—
28] and VT_LOPS_AIS_INH))
The output of the VT/TU mapper receive path will be as shown in
Figure 43 on page451
and
Figure 44 on
page 452
.
19.11 J2 Byte Monitor and Termination (J2MON)
The J2MON logic block (in
Figure 39 on page429
) will perform all necessary functions to monitor the incoming J2
trace identifier. The following features are implemented:
I
J2 monitoring will support five different monitoring modes defined by VT_J2MON_MODE[1
—
28][2:0]
Table 204
on pag e168
:
—
VT_J2MON_MODE[1
—
28][2:0] = 000: this mode captures an incoming 16-byte sequence and stores it in
VT_J2BYTE_DET[1
—
28][1
—
16][7:0] (
Table 209
). TIM-V is disabled for this mode.
—
VT_J2MON_MODE[1
—
28][2:0] = 001: this mode captures an incoming 16-byte sequence with SDH framing
and stores it in VT_J2BYTE_DET[1
—
28][1
—
16][7:0]. TIM-V is disabled for this mode.
—
VT_J2MON_MODE[1
—
28][2:0] = 010: this mode captures a constant 1-byte sequence and stores it in
VT_J2BYTE_DET[1
—
28][1][7:0]. TIM-V is disabled for this mode.
—
VT_J2MON_MODE[1
—
28][2:0] = 011: this mode monitors a 16-byte sequence with SDH framing and com-
pares it to a programmable expected value. The expected value is programmed by the user using register bits
VT_J2BYTE_EXP[1
—
28][1
—
16][7:0] (
Table 209
). The hardware frames by looking for the byte with the MSB
set to one, which indicates that the next byte is the second byte of the message. CRC is verified based on the
value programmed in VT_J2BYTE_EXP[1
—
28][1
—
16][7:0]. TIM-V is enabled for this mode.
—
VT_J2MON_MODE[1
—
28][2:0] = 100: this mode monitors a constant 1-byte sequence and compares it to an
programmable expected value. The expected value is programmed by the user using register bits
VT_J2BYTE_EXP[1
—
28][1][7:0]. TIM-V is enabled for this mode.
I
Trace identifier mismatch (TIM-V) will be detected following the number of consecutively errored sequences
(1-byte or 16-byte sequences) programmed in bits,
VT_
J2_NTIME[3:0] (
Table 183
), and reported to the micro-
processor via bit VT_J2TIM[1
—
28] (
Table 177
). If TIM-V is detected, the J2 byte monitor will transition into the
capture mode and start searching for two consecutive consistent 1-byte or 16-byte sequences. Once two con-
secutive consistent sequences are detected, the J2 byte monitor will transition into the monitor mode and start
searching for the number of consecutive mismatches programmed in register bits
VT_
J2_NTIME[3:0], on a per
1-byte or 16-byte sequence basis.
Once the hardware finds synchronization (
VT_
J2TIM[1
—
28] = 0), the new
sequence is latched into
VT_
J2BYTE_DET[1
—
28][1
—
16][7:0] (
Table 209
). The synchronization algorithm used
will not allow single bit errors to pass through to
VT_
J2BYTE_DET[1
—
28][1
—
16][7:0].