TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
80
Agere Systems Inc.
8 TMUX Registers
(continued)
Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW)
(continued)
Address
0x40006
Bit
7
Name
Function
Reset Default
0
TMUX_RF1MOND
Receive F1 Monitor Delta.
This delta bit indicates a
change in state of TMUX_RF1MON0[7:0] and
TMUX_RF1MON1[7:0] (
Table 101
) when a consistent
new value is detected in the incoming F1 byte for
TMUX_CNTDF1[3:0] (
Table 98
) continuous frames. The
current value is stored in TMUX_RF1MON0[7:0] and the
previous value is stored in TMUX_RF1MON0[7:0]. The
mask bit is TMUX_RF1MONM (
Table 86
).
TMUX_RTIMSD
Receive Section Trace Identifier Mismatch Delta.
This
delta bit indicates a change in state in the received 16-
byte J0 sequence of bytes if the J0 mode is programmed
to receive a 16-byte sequence. The mask bit is
TMUX_RTIMSM (
Table 86
).
TMUX_RHSSFD
Receive High-speed Signal Fail BER Algorithm Delta.
This delta bit indicates a change of state for the signal fail
BER algorithm state bit TMUX_RHSSF (
Table 91
). The
mask bit for this delta bit is TMUX_RHSSFM (
Table 86
).
TMUX_RHSSDD
Receive High-speed Signal Degrade BER Algorithm
Delta.
This delta bit indicates a change of state for the
signal degrade BER algorithm state bit TMUX_RHSSD
(
Table 91
). The mask bit is TMUX_RHSSDM (
Table 86
).
TMUX_RHSLOSD
Receive High-speed Loss of Signal Delta.
This delta
bit indicates a change in state of either TMUX_RHSLOS
(
Table 91
) or TMUX_RHSLOSEXTI (
Table 91
).
TMUX_RHSLOSEXTI is an external input from a device
pin. TMUX_RHSLOS is an internally generated state bit
based on monitoring for a consecutive 0/1s pattern in the
data input. The mask bit is TMUX_RHSLOSM (
Table 86
).
TMUX_RHSLOFD
Receive High-speed Loss of Frame Delta.
This delta
bit indicates a change in state of TMUX_RHSLOF
(
Table 91
). The mask bit is TMUX_RHSLOFM (
Table 86
).
TMUX_RHSOOFD
Receive High-speed Out of Frame Delta.
This delta bit
indicates a change in state of TMUX_RHSOOF
(
Table 91
). The mask bit is TMUX_RHSOOFM (
Table 86
).
TMUX_RHSILOCD
Receive High-speed Loss of Input Clock Delta.
This
delta bit indicates a change in state of the
TMUX_RHSILOC (
Table 91
) state bit. The mask bit is
TMUX_RHSILOCM (
Table 86
).
6
0
5
0
4
0
3
0
2
0
1
0
0
0