Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
215
Agere Systems Inc.
11 M13/M23 MUX/DeMUX Registers
(continued)
Table 256. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO)
Table 257. M13_DS2_FORCE_OOF_R, DS2 Force Out of Frame (One Shot R/W)
Table 258. M13_CONTROL1, Control 1 (One Shot R/W)
Address
Bit
Name
Address
Bit
Name
Function
Reset
Default
0x00
0x00
0x10055
15:8
7:0
—
Reserved.
This register provides information on the earliest HDLC frame
still in the FIFO. A value of 1 in bit 7 indicates that the closing
flag or an abort byte for the current frame has been received; a
1 in bit 6 indicates the current frame is corrupted; bits 5 to 1
indicate the size of the current frame modulo-32; and bit 0 is
set to 1 if there are less than 32 bytes of the earliest frame left
in the FIFO.
M13_RHDLC_
STATUS[7:0]
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10059
15:7
6:0
—
Reserved.
When M13_DS2_FORCE_OOFy transitions from 0 to 1, the
DS2 framer in M12 demultiplexer Y is forced out of frame.
M13_DS2_FORCE_
OOF[7:1]
Function
Reset
Default
0x000
0
0x1005A 15:3
—
Reserved.
If M13_RDL_FRM_CLR is set to 1, the portion of the earli-
est frame still in the receive HDLC FIFO will be deleted.
The user must reset M13_RDL_FRM_CLR before another
frame can be deleted. If M13_RDL_FRM_CLR is set before
the closing flag of the frame currently being read from the
FIFO has been received, all subsequent bytes of the frame
will be discarded without being written into the FIFO.
M13_DS3_FORCE_OOF When this bit transitions from 0 to 1, the DS3 framer is
forced out-of-frame.
M13_BIPOL_ERR
A single bipolar violation error is transmitted each time this
bit transitions from 0 to 1.
2
M13_RDL_FRM_CLR
1
0
0
0
Table 259. M13_CONTROL2, Control 2 (R/W)
Address
Bit
Name
Function
Reset
Default
0x00
0
0x1005C 15:8
—
Reserved.
If this bit is 1, the SMPR_RDS3NEG_BPV input is used as an
external B3ZS bipolar violation indication instead of a negative
input pulse.
The M23 multiplexer uses the SMPR_TDS3CLK if this bit is 0,
otherwise, the SMPR_RDS3CLK is used.
M13_LOOP_T_TO_R Setting this bit to 1 causes the M23 MUX output to be looped
back to the M23 DEMUX input.
M13_LOOP_R_TO_T Setting this bit to 1 causes the received DS3 input to be
looped back to the transmit DS3 output.
7
M13_BPV_IN
6
M13_LOOP_TIME
0
5
0
4
0