TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
486
Agere Systems Inc.
21 28-Channel Framer Block Functional Description
(continued)
21.3.3 Transmit Framer Functions
1. Transmits alarm indication signal (AIS) to the line automatically and on demand.
2. Transmits AIS-CI to the line automatically and on demand.
3. Transmits remote alarm indication (RAI) to the line automatically and on demand. Conditions for transmitting
RAI include; loss of received frame alignment, CEPT loss of received time slot 0 multiframe alignment, CEPT
CRC-4 timer expiration, CEPT loss of received time slot 16 signaling multiframe alignment, CEPT received Sa6
equals 8, and received Sa6 equals C.
4. Transmits RAI-CI to the line automatically and on demand.
5. Transmits auxiliary test pattern (AUXP) to the line automatically and on demand.
6. Transmits CEPT E bits based received CRC-4 errors.
7. Support the CEPT double not-FAS system mode.
8. Transmits a PRBS test pattern to the line on demand.
9. Transmits line loopback on and off codes to the line on demand (T1.403 section 9.3.1).
10. In transport mode, when not in frame alignment, to optionally send AIS or transparently pass data.
21.3.4 Framing References/Standards
1. ANSIT1.403, 1997.
2. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces; 1991.
3. ITU-T Recommendation G.704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488 and
44736 kbits/s Hierarchical Levels; July 1995.
4. ITU-T Recommendation G.706, Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to
Basic Frame Structures defined in Recommendation G.704; 1991.
5. TTC Standard JT-G704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488 and 44736 kbits/s Hier-
archical Levels; July 1995.
21.4 DS1 Transparent Framing Format
The transmit framer can be programmed to transparently transmit 193 bits of CHI system data to the line.
When configured for transparent framing, the transmit framer extracts from the receive CHI system data bit 8 of
time slot 1 and inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive
system time slot 1 are ignored by the transmit framer. The receive framer will extract the framing bit (or 193rd bit) of
the receive line data and insert it into bit 8 of time slot 1 of the CHI system data. The other bits of time slot 1 are set
to 0.
Frame integrity is maintained in both the transmit and receive framer sections.
5-5989(F).ar.1
Figure 58. DS1 Transparent Frame Structure
TIME-SLOT 1
(STUFF TIME-SLOT)
32 TIME-SLOT CHI FRAME
TIME-SLOT 2
TIME-SLOT 3
TIME-SLOT 31 TIME-SLOT 32
0
0
0
0
0
0
0
F BIT
TRAMSMIT FRAMER
’
S
193-bit FRAME
DS1 = 125
μ
s
TIME-SLOT 1 TIME-SLOT 2
TIME-SLOT 24
F BIT