Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
125
Agere Systems Inc.
8 TMUX Registers
(continued)
Table 143. TMUX Register Map
(continued)
Note:
The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State and Value Parameters
—
RO
0x40012
TMUX_TX_ST
ATE
TMUX_THS
ILOF
TMUX_THS
ILOC
0x40013
TMUX_RPS_
STATE
TMUX_RP
SLOF
TMUX_RP
SOOF
TMUX_RP
SILOC
0x40014
TMUX_RHS_
STATE
TMUX_RLR
DIMON
TMUX_RLA
ISMON
TMUX_RH
SLOSEXTI
TMUX_RTI
MS
TMUX_RH
SSF
TMUX_RH
SSD
TMUX_RH
SLOS
TMUX_RH
SLOF
TMUX_RH
SOOF
TMUX_RH
SILOC
0x40015
TMUX_RPOH
1_STATE
TMUX_RS
FB31
TMUX_RS
DB31
TMUX_RU
NEQP1
TMUX_RPL
MP1
TMUX_RTI
MP1
TMUX_RPA
IS1
TMUX_RL
OP1
0x40016
TMUX_RPOH
2_STATE
TMUX_RS
FB32
TMUX_RS
DB32
TMUX_RU
NEQP2
TMUX_RPL
MP2
TMUX_RTI
MP2
TMUX_CONCAT_STATE2
[1:0]
TMUX_RPA
IS2
TMUX_RL
OP2
0x40017
TMUX_RPOH
3_STATE
TMUX_RS
FB33
TMUX_RS
DB33
TMUX_RU
NEQP3
TMUX_RPL
MP3
TMUX_RTI
MP3
TMUX_CONCAT_STATE3
[1:0]
TMUX_RPA
IS3
TMUX_RL
OP3
Receive High-speed Control Parameters
—
R/W
0x40019
TMUX_RHS_
CTL
TMUX_LOS
EXT_LEVE
L
TMUX_RP
SMUXSEL1
TMUX_THS
2RHSLB
TMUX_RH
SDSCR
Receive Low-speed Control Parameters
—
R/W
0x4001A
TMUX_RLS_
BITBLK_CTL
TMUX_RCV_SS_EXP[1:0
]
TMUX_RC
V_SS_ENB
TMUX_BIT
BLKG1
TMUX_BIT
BLKM1
TMUX_BIT
BLKB3
TMUX_BIT
BLKB2
TMUX_BIT
BLKB1
0x4001B
TMUX_RLS_
MODE_CTL
TMUX_RPA
IS_INS
TMUX_8O
RMAJOR-
ITY
TMUX_SD
B1B2SEL
TMUX_SFB
1B2SEL
TMUX_J1MONMODE[2:0]
TMUX_J0MONMODE[2:0]
TMUX_S1
MODE4
TMUX_RLS
PAROEG
TMUX_
RCONCAT-
MODE
TMUX_
REPRDI_
MODE
0x4001C
TMUX_RAISI
NH_CTL
TMUX_R_
M1_BIT7
TMUX_
RSDB3_
AISINH
TMUX_RSF
B3_AISINH
TMUX_RTIMP_AISINH[3:1]
TMUX_
RUNEQP_
AISINH
TMUX_RPL
MP_AISINH
TMUX_
RHSSD_
AISINH
TMUX_
RHSSF_
AISINH
TMUX_
RPAISLOP
_AISINH
TMUX_
RLAISMON
_AISINH
TMUX_RL
OF_AISINH
TMUX_RO
OF_AISINH
TMUX_
RHSLOS_
AISINH
TMUX_RIL
OC_AISINH
0x4001D
TMUX_LOSD
ETCNT
TMUX_FORCEC2DEF[2:0]
TMUX_LOSDETCNT[10:0]
Continuous N-Times Detect Values
—
R/W
0x4001E
TMUX_CNTD
_TOH_A
TMUX_CNTDK1K2FRAME[3:0]
TMUX_CNTDK1K2[3:0]
TMUX_CNTDF1[3:0]
TMUX_CNTDJ0[3:0]
0x4001F
TMUX_CNTD
_TOH_B
TMUX_CTDLOPCNT[1:0]
TMUX_CNTDS1FRAME[3:0]
TMUX_CNTDS1[3:0]
TMUX_CNTDK2[3:0]
0x40020
TMUX_CNTD
_POH_A
TMUX_CNTDF2[3:0]
TMUX_CNTDRDIP[3:0]
TMUX_C2[3:0]
TMUX_CNTDJ1[3:0]
0x40021
TMUX_CNTD
_POH_B
TMUX_CT
DB1SEL
TMUX_CNTDN1[3:0]
TMUX_CNTDK3[3:0]
TMUX_CNTDF3[3:0]
0x40022
TMUX_C2EX
P1
TMUX_C2EXP1[7:0]
0x40023
TMUX_C2EX
P2_3
TMUX_C2EXP3[7:0]
TMUX_C2EXP2[7:0]