Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
541
Agere Systems Inc.
21 28-Channel Framer Block Functional Description
(continued)
21.29 Superframer Register Addressing
Table 609 below summarizes the address map for the global and per link/channel registers of the superframer:
Table 609. Framer Addressing Map for the Global and Per Link/Channel Registers of the Superframer
21.29.1 Per Link Register Sections in Table 609
SIG = Signaling (see
Section 12.9.1 Signaling Per Link Registers on page 267
).
PM = Performance Monitor (see
Section 12.3 Performance Monitor Global Registers on page 247
).
RDL = Receive (Facility) Data Link (see
Section 12.11 Receive Facility Data Link Configuration and Status Registers on
page 288
).
TDL = Transmit (Facility) Data Link (see
Section 12.12 Transmit Facility Data Link Configuration and Status Registers on
page 290
).
SYS = System Interface (see
Section 12.13 System Interface, Arbiter, and Frame Formatter Mapping on page 292
).
AR = Arbiter (Framer) (see
Section 12.2 Arbiter (Framer) Global Registers on page 245
).
FF = Frame Formatter (Transmit Framer) (see
Section 12.16 Frame Formatter Per Link Registers on page 300
).
LC = Line Encoder/Decoders (see
Section 12.18 Line Encoder/Decoder Per Link Registers on page 303
); RXP = 0 for
the line encoder and TXP = 1 for the line decoder.
HDLC = High-Level Data Link Control (see
Section 12.19 HDLC Per Channel Configuration and Status Registers on
page 304
); RXP = 0 for the receive HDLC and TXP = 1 for the transmit HDLC.
RXP = High-Level Data Link Control (see
Table 432 on page304
) RXP = 0 for the receive HDLC and TXP = 1 for the
transmit HLDLC.
Address Pins (ADDR15
—
ADDR0)
9
8
7
Framer Global Registers
0
RXP=0/
TXP=1
0
0
0
0
0
0
0
15
0
14
13
12
11
10
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Superframer Global
AR (Framer)
Performance Monitor
Performance Monitor
HDLC
System Interface
Signaling
Frame Formatter
(Transmit Framer)
Reserved
Receive Data Link
Transmit Data Link
Reserved
1
1
1
1
0
0
0
0
0
1
0
1
0
Others
0
Links 1
—
28 (00001
—
11100)
LNK4 LNK3 LNK2 LNK1
Framer Functional Register Addresses
SIG6
SIG5
SIG4
0
PM5
PM4
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
LNK0
0
1
1
1
1
1
1
1
1
SIG3
PM3
RDL3
TDL3
0
0
0
1
1
SIG2
PM2
RDL2
TDL2
SYS2
0
1
0
1
SIG1
PM1
RDL1
TDL1
SYS1
AR1
FF1
Res.
LC1
SIG0
PM0
RDL0
TDL0
SYS0
AR0
FF0
Res.
LC0
1
HDLC Channels 1
—
64 (000000
—
111111)
HDL9 HDL8 HDL7 HDL6
RXP=0/
TXP=1
Per Channel Register
HDL3
HDL2
HDL5
HDL4
HDL1
HDL0