TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
120
Agere Systems Inc.
8 TMUX Registers
(continued)
Table 127. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO)
Table 128. TMUX_G1ECNT[1
—
3], Receive G1 Error Counts (RO)
Address
Bit
Name
Function
Reset
Default
0x000
0x00000
0x4006C
0x4006C
—
0x4006D
15:2
1:0
15:0
—
Reserved.
Receive Line REI Count.
Counts the number of
errors received in the M1 byte of the receive
STS-3/STM-1 (AU-4) frame. This counter can either
count actual errors or block errors; see
TMUX_BITBLKM1 (
Table 95
). This counter holds at
its maximum value or rolls over depending on the
value of SMPR_SAT_ROLLOVER and transfers its
internal count to a holding register when
SMPR_PMRESET
transitions from a logic 0 to 1.
TMUX_M1ECNT[17:16]
—
TMUX_M1ECNT[15:0]
Address
Bit
Name
Function
Reset
Default
0x0000
0x4006E
15:0 TMUX_G1ECNT1[15:0]
Receive Path REI Count for Port 1.
Counts the number of
B3 errors received in the G1[7:4] bits of port 1 in the
received STS-3/STM-1 (AU-4) frame. This counter can
either count actual errors or block errors; see
TMUX_BITBLKB3 (
Table 95
). This counter holds at its max-
imum value or rolls over depending on the value of
SMPR_SAT_ROLLOVER (
Table 67
) and transfers its inter-
nal count to a holding register when SMPR_PMRESET
(
Table 65
) transitions from a logic 0 to 1.
15:0 TMUX_G1ECNT2[15:0]
Receive Path REI Count for Port 2.
Counts the number of
B3 errors received in the G1[7:4] bits of port 2 in the
received STS-3/STM-1 (AU-4) frame. This counter can
either count actual errors or block errors; see
TMUX_BITBLKB3 (
Table 95
). This counter holds at its max-
imum value or rolls over depending on the value of
SMPR_SAT_ROLLOVER and transfers its internal count to
a holding register when SMPR_PMRESET
transitions from
a logic 0 to 1.
15:0 TMUX_G1ECNT3[15:0]
Receive Path REI Count for Port 3.
Counts the number of
B3 errors received in the G1[7:4] bits of port 3 in the
received STS-3/STM-1 (AU-4) frame. This counter can
either count actual errors or block errors; see
TMUX_BITBLKB3 (
Table 95
). This counter holds at its max-
imum value or rolls over depending on the value of
SMPR_SAT_ROLLOVER and transfers its internal count to
a holding register when SMPR_PMRESET
transitions from
a logic 0 to 1.
0x4006F
0x0000
0x40070
0x0000