Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
331
Agere Systems Inc.
14 Digital Jitter Attenuation Controller Registers
Table of Contents
Contents
Page
14 Digital Jitter Attenuation Controller Registers .................................................................................................331
14.1 Digital Jitter Attenuation Controller Register Descriptions .......................................................................332
14.2 Digital Jitter Attenuation Controller Register Map ...................................................................................335
Tables
Page
Table 468. DJA_VERSION, DJA Version and Identification (RO) .......................................................................332
Table 469. DJA_EVENT1
—
DJA_EVENT2, Loss of Clock and Overflow/Underflow Delta
(COR/COW) .......................................................................................................................................332
Table 470. DJA_MASK1
—
DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W) .........................332
Table 471. DJA_STATE1
—
DJA_STATE2, Loss of Clock and VT Pointer Adjustment Indicators
(R/W) ..................................................................................................................................................333
Table 472. DJA_E1GAINH
—
DJA_E1GAINL, E1 Accumulator Gain Threshold (R/W) ........................................333
Table 473. DJA_DS1GAINH
—
DJA_DS1GAINL, DS1 Accumulator Gain Threshold (R/W) ................................333
Table 474. DJA_E1SCALE, E1 Scale Factor (R/W) ............................................................................................333
Table 475. DJA_DS1SCALE, DS1 Scale Factor (R/W) .......................................................................................333
Table 476. DJA_E1PTRH
—
DJA_E1PTRL, E1 First-Order Loop Counter (R/W) ...............................................334
Table 477. DJA_DS1PTRH
—
DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W) ........................................334
Table 478. DJA_DS1SELH
—
DJA_DS1SELL, DS1 E1 Mode Select (R/W) .......................................................334
Table 479. DJA_CLK_CTL1
—
DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W) ...............334
Table 480. DJA Register Map ..............................................................................................................................335