TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
206
Agere Systems Inc.
11 M13/M23 MUX/DeMUX Registers
(continued)
Table 225. M13_DS3_STATUS2, Status (RO)
Table 226. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO)
Table 227. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO)
Address
Bit
Name
Function
Reset
Default
000000
000
0
0
0x10010
15:7
—
Reserved.
6
5
M13_RDL_FIFO_UF
M13_RDL_FIFO_AF
This bit is 1 if the receive HDLC FIFO is underflow.
This bit is 1 if the number of unread bytes in the receive
HDLC FIFO is greater than the fill-up level set by bits
M13_RDL_FILL[1:0] (
Table 287
).
This bit is 1 if there are three or more F-bit errors in
16 consecutive F bits. It is not terminated until the signal is
in-frame and there are less than three F-bit errors in 16 con-
secutive F bits.
M13_RDS3_ALL1_DET This bit is 1 if the input data is 0 for fewer than 9 out of
8192 clock periods.
M13_RDS3_LOS
This bit is 1 if there are 175 ±75 contiguous pulse positions
with no pulses of either positive or negative polarity at the
DS3 Input. An LOS is cleared upon detecting an average
pulse density of at least 33% over a period of
175 ±75 contiguous pulse positions, starting with the receipt
of a pulse.
M13_TDS3_LOC
This bit is 1 if the SMPR_TDS3CLK
signal fails to have tran-
sitions for at least 10 periods of SMPR_RDS3CLK. A single
transition on SMPR_TDS3CLK resets this bit.
M13_RDS3_LOC
This bit is 1 if the SMPR_RDS3CLK signal fails to have tran-
sitions for at least 10 periods of SMPR_TDS3CLK. A single
transition on SMPR_RDS3CLK resets this bit.
4
M13_RDS3_SEF
1
3
0
2
0
1
0
0
0
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10011
15:7
6:0
—
Reserved.
These individual delta bits are set as the result of the corre-
sponding state bits M13_XC_DS2_LOC[7:1] (
Table 238
) transi-
tioning either from 0 to 1 or from 1 to 0. They can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
M13_XC_DS2_
LOCD[7:1]
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10012
15:7
6:0
—
Reserved.
These individual delta bits are set as the result of the corre-
sponding state bits M13_XC_DS2_AIS_DET[7:1]
(
Table 239
) transitioning either from 0 to 1 or from 1 to 0.
They can be programmed to be either clear on read (COR)
or clear on write (COW), and they are not set to 1 again until
the event reoccurs.
M13_XC_DS2_
AIS_DETD[7:1]