TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
574
Agere Systems Inc.
24 Test-Pattern Generation/Detection Functional Description
Table of Contents
Contents
Page
24 Test-Pattern Generation/Detection Functional Description ............................................................................ 574
24.1 Test-Pattern Generator Introduction ....................................................................................................... 575
24.2 Features ................................................................................................................................................. 575
24.3 Applications ............................................................................................................................................ 575
24.4 Block Diagram ........................................................................................................................................ 576
24.5 Functional Descriptions .......................................................................................................................... 576
24.5.1 Test-Pattern Generation .............................................................................................................. 576
24.5.2 TPG Clock Source ....................................................................................................................... 577
24.5.3 TPG Transmit Edge Select .......................................................................................................... 577
24.5.4 TPG Test-Pattern Framing .......................................................................................................... 577
24.5.5 DS1 TPG Framing ....................................................................................................................... 577
24.5.6 E1 TPG Framing ......................................................................................................................... 577
24.5.7 DS2 TPG Framing ....................................................................................................................... 578
24.5.8 DS3 TPG Framing ....................................................................................................................... 578
24.5.9 Line Encoding/Decoding ............................................................................................................. 578
24.5.10 TPG Test-Pattern Sequences ................................................................................................... 578
24.5.11 TPG Idle Generator ................................................................................................................... 579
24.5.12 TPG Error Insertion ................................................................................................................... 579
24.5.13 TPG Interrupts ........................................................................................................................... 579
24.5.14 Test-Pattern Monitor (TPM) ....................................................................................................... 579
24.5.15 TPM Channel Selection ............................................................................................................. 579
24.5.16 TPM Clock Edge and Data Polarity Selection ........................................................................... 579
24.6 TPM Framing Acquisition and Synchronization ...................................................................................... 579
24.6.1 DS1/E1 ........................................................................................................................................ 579
24.6.2 TPM Error Detection and Counting ............................................................................................. 580
24.6.3 TPM Interrupts ............................................................................................................................. 581
24.7 Microprocessor Interface ........................................................................................................................ 581
24.7.1 Microprocessor Interface Register Map ...................................................................................... 581
Figures
Page
Figure 100. TPG Block Interface Block Diagram.................................................................................................. 576
Tables
Page
Table 624. TPG Framing Controls (TPG_FRAMEx = 1) ..................................................................................... 577
Table 625. TPG Test-Pattern Sequences ........................................................................................................... 578
Table 626. TPM Interrupts ................................................................................................................................... 581