TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
250
Agere Systems Inc.
12 28-Channel Framer Registers
(continued)
Table 318. FRM_PMGR8, Performance Monitor Global Register 8 (R/W)
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 319. FRM_PMGR9, Performance Monitor Global Register 9 (R/W)
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 320. FRM_PMGR10, Performance Monitor Global Register 10 (R/W)
These bits enable the errored events used to determine errored and severely errored seconds in the CEPT modes.
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 321. FRM_PMGR11, Performance Monitor Global Register 11 (R/W)
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Address
*
Bit
Name
Function
Reset
Default
0x0393
0x80P37
15:0
FRM_CCT[15:0]
CEPT Excessive CRC Threshold
—
Default 915.
This register
sets the one second CRC threshold at which an excessive CRC
error condition is reported and the one second CRC threshold at
which a reframe may be forced.
Address
*
Bit
Name
Function
Reset
Default
0x0000
0x80P38
15:0 FRM_CSEST[15:0]
CEPT Severely Errored Second Threshold for All CEPT
Formatted Channels.
Address
*
Bit
Name
Function
Reset
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0x80P39
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FRM_CSA6_F
FRM_CSA6_E
FRM_CSA6_C
FRM_CSA6_8
FRM_CSA6_1X
CEPT Sa6 = 001x Event Enable.
FRM_CSA6_X1
CEPT Sa6 = 00x1 Event Enable.
FRM_CEBIT
CEPT E bit = 0 Event Enable.
FRM_CLMFA
CEPT Loss of Multiframe Alignment Enable.
FRM_CLFA
CEPT Loss of Frame Alignment Enable.
FRM_CRFA
CEPT Remote Frame Alarm Enable.
FRM_CSLIP
CEPT Slip Enable.
FRM_CLOS
CEPT Loss of Signal Enable.
FRM_CAIS
CEPT Alarm Indication Signal Enable.
FRM_CCRC
CEPT CRC-4 Error Enable.
FRM_CNOTFAS
CEPT Non-FAS Bit Error Enable.
FRM_CFAS
CEPT FAS Bit Error Enable.
CEPT Sa6 = F Enable and Sa5 = 1.
(Reception of AIS.)
CEPT Sa6 = E Enable and Sa5 = 1.
(FC3 and FC4.)
CEPT Sa6 = C Enable and Sa5 = 1.
(LOS/LFA.)
CEPT Sa6 = 8 Enable and Sa5 = 1.
(Loss of power.)
Address
*
Bit
Name
Function
Reset
Default
0x03DF
0x80P3A
15:0
FRM_CRET[15:0]
Continuous Received E-Bit Threshold
—
Default 991.
This
register sets the five second continuous E-bit threshold for set-
ting the CRE bit status indication.