15
Agere Systems Inc.
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
(continued)
3.3 Pin Descriptions
3.3.1 High-speed I/O Pin Descriptions
The high speed I/O consists of five LVDS signals (10 pins) that connect the Super Mapper to an external OC-3
optics device. It exchanges an STS-3 or STM-1 signal between the TMUX and an OC-3 transceiver. The Super
Mapper is capable of recovering a clock from the receive data, or can accept a clock recovered externally by the
optics device. If internal clock recovery is used, the Super Mapper uses THSCP/N as a reference.
The high-speed I/O may also run at 52.84 Mbits/s in applications that terminate an STS-1 or EC-1 signal. In this
case, the (electrical) line signals are typically terminated by a line interface unit (LIU) chip. The operating speed of
the high-speed I/O is determined by TMUX_RCV_TX_MODE.
Table 3. High-speed I/O Pin Descriptions
Pin
AF7,
AE7
Symbol
RHSDP
RHSDN
Type
LVDS
I/O
I
Description
Receive High-speed Data.
155.52 Mbits/s serial data input in STS-1 or
STM-1 format, or 51.84 Mbits/s data in STS-1 format. If RHSD is not used
(in a slave Super Mapper, for example) the P input should be pulled high
through a 1 k
resistor and the N input pulled low through a 1 k
resistor.
RHSD is typically provided by and OC-3 receiver, an STS-1 line interface
unit or an higher order (e.g. STS-12) demultiplexing chip.
Receive High-speed Clock.
155.52 or 51.84 MHz clock for STS-3 or
STS-1 input data. Typically supplied by an external OC-3 opto-electonic
device, or an STS-1/EC1 line interface unit, synchronous with RHSD. If
the internal clock recovery (CDR) feature is enabled, RHC is not required
and should be connected to through 1 k
resistors to V
DD
(RHCP input)
and V
SS
(RHCN input).
Transmit High-speed Clock.
Transmit 155.52 MHz or 51.84 MHz clock.
Master clock for the transmit sections of the TMUX, telecom bus, SPE,
and VT mappers. THSC is also used as a reference clock for the receive
CDR, if it is being used.
Transmit High-speed Frame Synchronization.
An optional input that
may be used to specify the position of the transmit STS-3, STM-1, or
STS-1 frame. THSSYNC marks the position of bit 1 of the A1 byte, i.e.,
the first bit of the overhead in the THSD output. If THSSYNC is not used,
the P input should be pulled high through a 1 k
resistor, and the N input
pulled low through a 1 k
resistor. A typical application for this pin may be
to synchronize a group of Super Mappers, so that their STS-3 outputs
may be multiplexed into an STS-12 signal.
Transmit High-speed Data.
Transmit output for STS-3, STM-1, or STS-1
serial data. Typically connected to an OC-3 module or an LIU, if operating
in STS-1 mode. May also be connected to a higher order multiplexing
device, STS-12 for example.
AC7,
AD8
RHSCP
RHSCN
LVDS
I
AF8,
AE8
THSCP
THSCN
LVDS
I
AC8,
AD9
THSSYNCP
THSSYNCN
LVDS
I
AF9,
AE9
THSDP
THSDN
LVDS
O