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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 108/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
exact number of clock cycles for any particular access
will depend upon the relative phases of the signal on
the BCLK pin and the internal clock that is used to drive
the PCnet-32 controller buffer management unit. Since
the PCnet-32 controller buffer management unit
operates on a clock that is a
÷
2 version of the interface
clock, it possible for the buffer management unit to
introduce one or more BCLK wait delays to allow for
synchronization of the two state machines before proceeding
with the access. The PCnet-32 buffer management unit
uses BCLK
÷
2, so the maximum number of BCLK
cycles needed to synchronize the BIU and buffer
management units is one BCLK period.
APROM Access
The APROM space is a convenient place to store the
value of the IEEE station address. This space is auto-
matically loaded from the serial EEPROM, if an
EEPROM is present. Its contents have no effect on the
operation of the controller. The software must copy the
station address from the APROM space to the
Initialization Block or to CSR12
–
CSR14 in order for the
receiver to accept unicast frames directed to this
station.
When programmed for WIO mode, any byte or word
address from an offset of 0h to an offset of Fh may be
read. An appropriate byte or word of APROM contents
will be delivered by the PCnet-32 controller in response
to accesses that fall within the APROM range of 0h to
Fh.
When programmed for DWIO mode, only double word
addresses from an offset of 0h to an offset of Fh may
be read. An appropriate double word of APROM
contents will be delivered in response to accesses that
fall within the APROM range of 0h to Fh.
Reads of non-double-word
quantities
are not allowed in
DWIO mode, even though such an access may be
properly aligned to a double word address boundary.
Write access to any of the APROM locations is allowed,
but only 4 bytes on double-word boundaries in DWIO
mode or 2 bytes on word boundaries in WIO mode. The
IESRWE bit (see BCR2) must be set in order to enable
such a write. Only the PCnet-32 controller on-board
IEEE Shadow registers are modified by writes to
APROM locations. The EEPROM is unaffected by
writes to APROM locations.
Note that the APROM locations occupy 16 bytes of
space, yet the IEEE station address requirement is for
6 bytes. The 6 bytes of IEEE station address occupy
the first 6 locations of the APROM space. The next six
bytes are reserved. Bytes 12 and 13 should match the
value of the checksum of bytes 1 through 11 and 14
and 15. Bytes 14 and 15 should each be ASCII
“
W
”
(57
h) if compatibility to AMD driver software is desired.
RDP Access (CSR Register Space)
RDP = Register Data Port. The RDP is used with the
RAP to gain access to any of the PCnet-32 controller
CSR locations.
Access to any of the CSR locations of the PCnet-32
controller is performed through the PCnet-32
controller
’
s Register Data Port (RDP). In order to
access a particular CSR location, the Register Address
Port (RAP) should first be written with the appropriate
CSR address. The RDP now points to the selected
CSR. A read of the RDP will yield the selected CSR
’
s
data. A write to the RDP will write to the selected CSR.
When programmed for WIO mode, the RDP has a
width of 16 bits, hence, all CSR locations have 16 bits
of width. Note that when accessing RDP, the upper two
bytes of the data bus will be undefined since the byte
masks will not be active for those bytes.
If DWIO mode has been invoked, then the RDP has a
width of 32 bits, hence, all CSR locations have 32 bits
of width and the upper two bytes of the data bus will be
active, as indicated by the byte mask. In this case, note
that the upper 16 bits of all CSR locations (except
CSR88) are reserved and written as zeros and read as
undefined values. Therefore, during RDP write opera-
tions in DWIO mode, the upper 16 bits of all CSR loca-
tions should be written as ZEROs.
RAP Access
RAP = Register Address Port. The RAP is used with
the RDP and with the BDP to gain access to any of the
CSR and BCR register locations, respectively. The
RAP contains the address pointer that will be used by
an access to either the RDP or BDP. Therefore, it is
necessary to set the RAP value before accessing a
specific CSR or BCR location. Once the RAP has been
written with a value, the RAP value remains unchanged
until another RAP write occurs, or until an H_RESET or
S_RESET occurs. RAP is set to all zeros when an
H_RESET or S_RESET occurs. RAP is unaffected by
the STOP bit.
When programmed for WIO mode, the RAP has a width
of 16 bits. Note that when accessing RAP, the lower two
bytes of the data bus will be undefined since the byte
masks will not be active for those bytes
When programmed for DWIO mode, the RAP has a
width of 32 bits. In DWIO mode, the upper 16 bits of the
RAP are reserved and written as zeros and read as un-
defined. These bits should be written as zeros.
BDP Access (BCR Register Space)
BDP = Bus Configuration Register Data Port. The BDP
is used with the RAP to gain access to any of the
PCnet-32 controller BCR locations.
Access to any of the BCR locations of the PCnet-32
controller is performed through the PCnet-32
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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