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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 90/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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90
Am79C965A
tion), perform a single-cycle DMA transfer to update the
status of the first descriptor (reset the OWN bit in
TMD1), and then it may perform one data DMA access
on the second buffer in the chain before executing an-
other look-ahead operation (i.e. a look-ahead to the
third descriptor.)
The PCnet-32 controller can queue up to two frames in
the transmit FIFO. Call them frame
“
X
”
and frame
“
Y
”
,
where
“
Y
”
is after
“
X
”
. Assume that frame
“
X
”
is
currently being transmitted. Because the PCnet-32
controller can perform look-ahead data transfer past
the ENP of frame
“
X
”
, it is possible for the PCnet-32
controller to completely transfer the data from a buffer
belonging to frame
“
Y
”
into the FIFO even though frame
“
X
”
has not yet been completely transmitted. At the end
of this
“
Y
”
buffer data transfer, the PCnet-32 controller
will write intermediate status (change the OWN bit to a
zero) for the
“
Y
”
frame buffer, if frame
“
Y
”
uses data
chaining. The last TDTE for the
“
X
”
frame (containing
ENP) has not yet been written, since the
“
X
”
frame has
not yet been completely transmitted. Note that the
PCnet-32 controller has, in this instance, returned
ownership of a TDTE to the host out of a
“
normal
”
sequence. For this reason, it becomes imperative that
the host system should never read the Transmit DTE
ownership bits out of order.
There should be no problems for software which proc-
esses buffers in sequence, waiting for ownership
before proceeding.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, then
TMD2 and TMD1 of the current buffer will be written. In
such a case, data transfers from the next buffer will not
commence. Instead, following the TMD2/TMD1
update, the PCnet-32 controller will go to the next
transmit frame, if any, skipping over the rest of the
frame which experienced an error, including chained
buffers. This is done by returning to the polling
microcode where PCnet-32 controller will immediately
access the next descriptor and find the condition
OWN=1 and STP=0 as described earlier. As described
for that case, the PCnet-32 controller will reset the own
bit for this descriptor and continue in like manner until
a descriptor with OWN=0 (no more transmit frames in
the ring) or OWN=1 and STP=1 (the first buffer of a new
frame) is reached.
At the end of any transmit operation, whether
successful or with errors, immediately following the
completion of the descriptor updates, the PCnet-32
controller will al ways perform another poll operation.
As described earlier, this poll operation will begin with
a check of the current RDTE, unless the PCnet-32
controller already owns that descriptor. Then the
PCnet-32 controller will proceed to polling the next
TDTE. If the transmit descriptor OWN bit has a zero
value, then the PCnet-32 controller will resume poll
time count incrementing. If the transmit descriptor
OWN bit has a value of ONE, then the PCnet-32
controller will begin filling the FIFO with transmit data
and initiate a transmission. This end-of-operation poll
coupled with the TDTE look-ahead operation allows
the PCnet-32 controller to avoid inserting poll time
counts between successive transmit frames.
Whenever the PCnet-32 controller completes a
transmit frame (either with or without error) and writes
the status information to the current descriptor, then the
TINT bit of CSR0 is set to indicate the completion of a
transmission. This causes an interrupt signal if the
IENA bit of CSR0 has been set and the TINTM bit of
CSR3 is reset.
Receive Descriptor Table Entry (RDTE)
If the PCnet-32 controller does not own both the current
and the next Receive Descriptor Table Entry then the
PCnet-32 controller will continue to poll according to
the polling sequence described above. If the receive
descriptor ring length is 1, then there is no next
descriptor to be polled.
If a poll operation has revealed that the current and the
next RDTE belong to the PCnet-32 controller then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the PCnet-32 controller retains ownership of the
current and the next RDTE.
When receive activity is present on the channel, the
PCnet-32 controller waits for the complete address of
the message to arrive. It then decides whether to
accept or reject the frame based on all active
addressing schemes. If the frame is accepted the
PCnet-32 controller checks the current receive buffer
status register CRST (CSR41) to determine the
ownership of the current buffer.
If ownership is lacking, then the PCnet-32 controller will
immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the PCnet-32
controller has no buffer in which to store the incoming
message. The MISS bit will be set in CSR0 and an
interrupt will be generated if INEA=1 (CSR0) and
MISSM=0 (CSR3). Another poll of the current RDTE
will not occur until the frame has finished.
If the PCnet-32 controller sees that the last poll (either
a normal poll, or the last-ditch effort described in the
above paragraph) of the current RDTE shows valid
ownership, then it proceeds to a poll of the next RDTE.
Following this poll, and regardless of the outcome of
this poll, transfers of receive data from the FIFO may
begin.
Regardless of ownership of the second receive
descriptor, the PCnet-32 controller will continue to
perform receive data DMA transfers to the first buffer,
using burst-cycle DMA transfers. If the frame length
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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