Am79C965A
113
of the EEPROM data fails, then at the end of the
EEPROM read sequence, the PCnet-32 controller will
force all EEPROM-programmable register locations
back to their H_RESET default values and then the
PCnet-32 controller will enter Software Relocatable
Mode. The 8-bit checksum for the entire 36 bytes of the
EEPROM should be FFh. In the event of a checksum
failure, Software Relocatable Mode is entered
(PCnet-32 controller begins snooping for a 12-byte
sequence) within 1 EESK period following the de-
assertion of EECS
.
If the absence of an EEPROM has been signaled by
the EESK/LED1/SFBD pin at the time of the automatic
read operation, then the PCnet-32 controller will
recognize this condition and will abort the automatic
read operation and reset both the PREAD and PVALID
bits in BCR19. At this point, the PCnet-32 controller will
enter the Software Relocatable Mode, and the
EEPROM-programmable registers will be assigned
their H_RESET default values. Software Relocatable
Mode is entered (PCnet-32 controller begins snooping
for 12-byte sequence) within 2.5 EESK periods
following the de-assertion of the RESET pin when
absence of an EEPROM is signalled by the EESK/LEDI
SFBD pin.
If the user wishes to modify any of the configuration bits
that are contained in the EEPROM, then the 7 com-
mand, data and status bits of BCR19 can be used to
write to the EEPROM. After writing to the EEPROM,
the host should set the PREAD bit of BCR19. This
action forces a PCnet-32 controller re-read of the
EEPROM so that the new EEPROM contents will be
loaded into the EEPROM-programmable registers on
board the PCnet-32 controller. (The EEPROM-
programmable registers may also be reprogrammed
directly, but only information that is stored in the
EEPROM will be preserved at system power-down.)
When the PREAD bit of BCR19 is set, it will cause the
PCnet-32 controller to ignore further accesses on the
system interface bus until the completion of the
EEPROM read operation.
EEPROM Auto-Detection
The PCnet-32 controller uses the EESK/LED1/SFBD
pin to determine if an EEPROM is present in the
system. At all rising BCLK edges during the assertion
of the RESET pin, the PCnet-32 controller will sample
the value of the EESK/LED1/SFBD pin. If the sampled
value is a ONE, then the PCnet-32 controller assumes
that an EEPROM is present, and the EEPROM read
operation begins shortly after the RESET pin is de-
asserted. If the sampled value of EESK/LED1/SFBD is
a ZERO, then the PCnet-32 controller assumes that an
external pull-down device is holding the EESK/LED1/
SFBD pin low, and therefore, there is no EEPROM in
the system. In this case, the PCnet-32 controller will
enter Software Relocatable Mode. Note that if the
designer creates a system that contains an LED circuit
on the EESK/LED1/SFBD pin but has no EEPROM
present, then the EEPROM auto-detection function will
incorrectly conclude that an EEPROM is present in the
system. However, this will not pose a problem for the
PCnet-32 controller, since it will recognize the lack of
an EEPROM at the end of the read operation, when the
checksum verification fails. At this point, the PCnet-32
controller will enter Software Relocatable Mode.
The real intention of the EEPROM auto-detection fea-
ture is to allow a user to preempt a
“
good EEPROM
”
by
temporarily resistively shorting the EESK/LED1/SFBD
pin to ground. This may need to be done if an add-in
card containing the PCnet-32 controller and its
EEPROM has been programmed in one system and
then later moved to a different system without also
moving configuration information that indicates the I/O
Base address of the card. The card would power up in
the second system with an unknown I/O Base address
if the configuration information were not carried with
the card to the new system. By allowing the EESK/
LED1/SFBD pin to be temporarily resistively shorted to
ground, the PCnet-32 controller is fooled into believing
that the EEPROM does not exist, and it will enter
Software Relocatable Mode. This allows the new
system to reconfigure the I/O Base address of the
PCnet-32 controller to a location that is compatible to
the parameters of the new system. This information will
then be written into the EEPROM by a configuration
utility through the EEPROM access port (BCR19), in
spite of the fact that the PCnet-32 controller believes
that there is no EEPROM. The resistive short to ground
may now be removed, and the next power-up of the
system will place the PCnet-32 controller into a I/O
location that is known by this system. When the
PREAD bit of BCR19 is set, an EEPROM read
operation will be performed, regardless of the value of
the EESK/ LED1/SFBD pin. Note that the H_RESET-
generated EEPROM read operation always obeys the
EESK/ LED1/SFBD indication.
Table 38 indicates the possible combinations of EEDET
and the existence of an EEPROM and the resulting op-
erations that are possible on the EEPROM microwire
interface.
Note that the EEDET value (BCR19, bit 3) is
determined from EESK/LED1/SFBD pin setting, and it
may be set even though there is no EEPROM present.
1
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2.5
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