參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 41/228頁
文件大小： 1681K
代理商： AM79C965A
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Am79C965A
41
LEDPRE3
LEDPRE3
This pin is shared with the EEDO function. When operating
as LEDPRE3, the function and polarity on this pin are
programmable through BCR7. This signal is labeled as LED
“
PRE
”
3 because of the multi-function nature of this pin. If an
LED circuit were directly attached to this pin, it would create
an
IOL
requirement that could not be met by the serial
EEPROM that would also be attached to this pin. Therefore,
if this pin is to be used as an additional LED output while an
EEPROM is used in the system, then buffering is required
between the LEDPRE3 pin and the LED circuit. If no
EEPROM is included in the system design, then the
LEDPRE3 signal may be directly connected to an LED
without buffering. The LEDPRE3 output from the PCnet-32
controller is capable of sinking the necessary 12 mA of
current to drive an LED in this case. For more details
regarding LED connection, see the section on LEDs.
LNKST
LINK Status
This pin provides 12 mA for driving an LED. It indicates
an active link connection on the 10BASE-T interface.
The signal is programmable through BCR4. Note that
this pin is multiplexed with the EEDI function.
Output
Output
This pin remains active in snooze mode.
SHFBUSY
Shift Busy
The function of the SHFBUSY signal is to indicate
when the last byte of the EEPROM contents has been
shifted out of the EEPROM on the EEDO signal line.
This information is useful for
external EEPROM-
programmable registers
that do not use the microwire
protocol, as is described herein: When the PCnet-32
controller is performing a serial read of the EEPROM
through the microwire interface, the SHFBUSY signal
will be driven HIGH. SHFBUSY can serve as a serial
shift enable to allow the EEPROM data to be serially
shifted into an external device or series of devices. The
SHFBUSY signal will remain actively driven HIGH until
the end of the EEPROM read operation. If the
EEPROM checksum was verified, then the SHFBUSY
signal will be driven LOW at the end of the EEPROM
read operation. If the EEPROM checksum verification
failed, then the SHFBUSY signal will remain HIGH.
This function effectively demarcates the end of a
successful EEPROM read operation and therefore is
useful as a programmable-logic
low-active output
enable
signal. For more details on external EEPROM-
programmable registers, see the
EEPROM Microwire
Access
section under
Hardware Access
.
Output
This pin can be controlled by the host system by writing
to BCR19, bit 3 (EBUSY).
SLEEP
Sleep
When SLEEP input is asserted (active LOW), the
PCnet-32 controller performs an internal system reset
and then proceeds into a power savings mode. (The
reset operation caused by SLEEP assertion will not af-
fect BCR registers.) All outputs will be placed in their
normal reset condition. During sleep mode, all
PCnet-32 controller inputs will be ignored except for the
SLEEP pin itself. De-assertion of SLEEP results in
wake-up. The system must refrain from starting the
network operations of the PCnet-32 controller for 0.5
seconds following the de-assertion of the SLEEP
signal in order to allow internal analog circuits to
stabilize.
Input
Both BCLK and XTAL1 inputs must have valid clock
signals present in order for the SLEEP command to
take effect.
If SLEEP is asserted while LREQ/HOLD is asserted,
then the PCnet-32 controller will perform an internal
system reset and then wait for the assertion of LGNT/
HLDA. When LGNT/HLDA is asserted, the LREQ/
HOLD signal will be de-asserted and then the PCnet-
32 controller will proceed to the power savings mode.
Note that the internal system reset will not cause the
HOLD/LREQ signal to be de-asserted.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the
assertion of SLEEP until three BCLK cycles after the
completion of a valid pin RESET operation.
XTAL1
–
XTAL2
Crystal Oscillator Inputs
The crystal frequency determines the network data
rate. The PCnet-32 controller supports the use of
quartz crystals to generate a 20 MHz frequency
compatible with the ISO 8802-3 (IEEE/ANSI 802.3)
network frequency tolerance and jitter specifications.
See the section
External Crystal Characteristics
(in
section Manchester Encoder/ Decoder) for more detail.
Input/Output
The network data rate is one-half of the crystal fre-
quency. XTAL1 may alternatively be driven using an
external CMOS level source, in which case XTAL2
must be left unconnected. Note that when the
PCnet-32 controller is in coma mode, there is an
internal 22 KW resistor from XTAL1 to ground. If an
external source drives XTAL1, some power will be
consumed driving this resistor. If XTAL1 is driven LOW
at this time power consumption will be minimized. In
this case, XTAL1 must remain active for at least 30
cycles after the assertion of SLEEP and de-assertion
of HOLD.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
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AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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