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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 145/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
145
detected (regardless of length).
RCVFW is set to a value of 10 (64
bytes) after H_RESET or S_RESET
and is unaffected by STOP.
Read/write accessible only when
STOP bit is set.
Certain combinations of watermark
programming and LINBC (BCR18[2-
0]) programming may create
situations where no linear bursting is
possible, or where the FIFO may be
excessively read or excessively
written. Such combinations are
declared as illegal.
Combinations of watermark set-
tings and LINBC settings must obey
the following relationship:
watermark (in bytes)
LINBC (in
bytes)
Combinations of watermark and
LINBC settings that violate this rule
may cause unexpected behavior.
11-10 XMTSP[1:0]Transmit Start Point. XMTSP
controls the point at which pre-
amble transmission attempts
commence in relation to the number
of bytes written to the transmit FIFO
for the current transmit frame. When
the entire frame is in the FIFO,
transmission will start regardless of
the value in XMTSP. XMTSP is given
a value of 10 (64 bytes) after
H_RESET or S_RESET and is
unaffected by STOP. Regardless of
XMTSP, the FIFO will not internally
over write its data until at least 64
bytes (or the entire frame if <64
bytes) have been transmitted onto
the network. This ensures that for
collisions within the slot time
window, transmit data need not be
rewritten to the transmit FIFO, and
retries
autonomously by the MAC. This bit
is read/write accessible only when
the STOP bit is set.
will
be
handled
9-8
XMTFW[1:0] Transmit
XMTFW specifies the point at which
transmit DMA stops, based upon the
number of write cycles that could be
performed to the transmit FIFO
without FIFO overflow. Transmit
DMA is allowed at any time when the
number of write cycles specified by
SMTFW could be executed without
causing transmit FIFO overflow.
XMTFW is set to a value of 00b (8
cycles) after H_RESET or
S_RESET and is unaffected by
STOP. Read/write accessible only
when STOP bit is set.
FIFO
Watermark.
Certain combinations of watermark
programming
programming may create situations
where no linear bursting is possible,
or where the FIFO may be
excessively read or excessively
written. Such combinations are
declared as illegal.
and
LINBC
Combinations of watermark set-
tings and LINBC settings must obey
the following relationship:
watermark (in bytes)
LINBC (in
bytes)
Combinations of watermark and
LINBC settings that violate this rule
may cause unexpected behavior.
7-0
DMACR[7:0] DMA Cycle Register. This regis-
ter contains the maximum allow-
able number of transfers to system
memory that the Bus Interface will
perform during a single DMA cycle.
The Cycle Register is not used to
limit the number of transfers during
Descriptor transfers. A value of zero
will be interpreted as one transfer.
RCVFW[1:0]
Bytes Received
00
01
10
11
16
32
64
Reserved
XMTSP[1:0]
Bytes Written
00
01
10
11
4
16
64
112
XMTFW[1:0]
Write Cycles
00
01
10
11
8
16
32
Reserved
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| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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