參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 23/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
23
Attachment Unit Interface
CI±
Collision In
A differential input pair signaling the PCnet-32
controller that a collision has been detected on the
network media, indicated by the CI± inputs being
driven with a 10 MHz pattern of sufficient amplitude
and pulse width to meet ISO 8802-3 (IEEE/ANSI
802.3) standards. Operates at pseudo ECL levels.
DI±
Data In
A differential input pair to the PCnet-32 controller carry-
ing Manchester encoded data from the network. Oper-
ates at pseudo ECL levels.
DO±
Data Out
A differential output pair from the PCnet-32 controller
for transmitting Manchester encoded data to the
network. Operates at pseudo ECL levels.
Twisted Pair Interface
RXD±
10BASE-T Receive Data
10BASE-T port differential receivers.
TXD±
10BASE-T Transmit Data
10BASE-T port differential drivers.
TXP±
10BASE-T Pre-distortion Control
These outputs provide transmit predistortion control in
conjunction with the 10BASE-T port differential drivers.
External Address Detection Interface
The EADI interface is enabled through bit 3 of BCR2
(EADISEL).
EAR
External Address Reject Low
An EADI input signal. The incoming frame will be
checked against the internally active address detection
mechanisms and the result of this check will be OR
’
d
with the value on the EAR pin. The EAR pin is defined
as REJECT.
Input
Input
Output
Input
Output
Output
Input
See the EADI section for details regarding the function
and timing of this signal.
Note that this pin is multiplexed with the INTR2 pin.
SFBD
Start Frame
–
Byte Delimiter
Start Frame
–
Byte Delimiter Enable. EADI output
signal. An initial rising edge on this signal indicates that
a start of frame delimiter has been detected. The serial
bit stream will follow on the SRD signal, commencing
with the destination address field. SFBD will go high for
4 bit times (400 ns) after detecting the second
“
1
”
in the
SFD (Start of Frame Delimiter) of a received frame.
SFBD will subsequently toggle every 400 ns (1.25 MHz
frequency) with each rising edge indicating the first bit
of each subsequent byte of the received serial bit
stream. SFBD will be inactive during frame
transmission.
Output
Note that this pin is multiplexed with the LED1 pin.
SRD
Serial Receive Data
An EADI output signal. SRD is the decoded NRZ data
from the network. This signal can be used for external
address detection. Note that when the 10BASE-T port
is selected, transitions on SRD will only occur during
receive activity. When the AUI port is selected,
transitions on SRD will occur during both transmit and
receive activity.
Output
Note that this pin is multiplexed with the LEDPRE3 pin.
SRDCLK
Serial Receive Data Clock
An EADI output signal. Serial Receive Data is
synchronous with reference to SRDCLK. Note that
when the 10BASE-T port is selected, transitions on
SRDCLK will only occur during receive activity. When
the AUI port is selected, transitions on SRDCLK will
occur during both transmit and receive activity.
Output
Note that this pin is multiplexed with the LED2 pin.
General Purpose Serial Interface
The GPSI interface is selected through the PORTSEL
bits of the Mode register (CSR15) and enabled through
the TSTSHDW[1] bit (BCR18) or the CORETEST bit
(CSR124).
Note that when GPSI test mode is invoked, slave ad-
dress decoding must be restricted to the lower 24 bits
of the address bus by setting the IOAW24 bit in BCR2
and by pulling LED2 LOW during Software Relocatable
Mode. The upper 8 bits of the address bus will always
be considered matched when examining incoming I/O
addresses. During master accesses while in GPSI
mode, the PCnet-32 controller will not drive the upper
8 bits of the address bus with address information. See
the GPSI section for more detail.
相關PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關代理商/技術參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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