參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 16/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
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16
Am79C965A
Table 4. Configuration Pin Settings
*X = Don’t care
Pin Connections to
V
DD
or
V
SS
Several pins may be connected to V
DD
or V
SS
for
various application options. Some pins are required to
be connected to V
DD
or V
SS
in order to set the
controller into a particular mode of operation, while
other pins might be connected to V
DD
or V
SS
if that
pin
’
s function is not implemented in a specific
application. Table 5 shows which pins require a
connection to V
DD
or V
SS
, and which pins may
optionally be connected to V
DD
or V
SS
because the
application does not support that pin
’
s function. The
table also shows whether or not the connections need
to be resistive.
VESA VL-Bus Interface
ADR2
–
ADR31
Address Bus
Address information which is stable during a bus
operation, regardless of the source. When the
PCnet-32 controller is Current Master, A2
–
A31 will be
driven. When the PCnet-32 controller is not Current
Master, the A2
–
A31 lines are continuously monitored
to determine if an address match exists for I/O slave
transfers.
ADS
Address Status
When driven LOW, this signal indicates that a valid bus
cycle definition and address are available on the M/IO,
D/C, W/R and A2
–
A31 pins of the local bus interface.
At that time, the PCnet-32 controller will examine the
combination of M/IO, D/C, W/R, and the A2
–
A31 pins
to determine if the current access is directed toward the
PCnet-32 controller.
Input/Output
Input/Output
ADS will be driven LOW when the PCnet-32 controller
performs a bus master access on the local bus.
BE0
–
BE3
Byte Enable
These signals indicate which bytes on the data bus are
active during read and write cycles. When BE3 is
active, the byte on DAT31
–
DAT24 is valid. BE2
–
BE0
active indicate valid data on pins DAT23
–
DAT16,
DAT15
–
DAT8, DAT7
–
DAT0, respectively. The byte
enable signals are outputs for bus master and inputs for
bus slave operations.
BLAST
Burst Last
When the BLAST signal is asserted, then the next time
that BRDY or RDYRTN is asserted, the burst cycle is
complete.
BRDY
Burst Ready
BRDY functions as an input to the PCnet-32 controller
during bus master cycles. When BRDY is asserted
during a master cycle, it indicates to the PCnet-32
controller that the target device is accepting burst
transfers. It also serves the same function as RDYRTN
does for non-burst accesses. That is, it indicates that
the target device has accepted the data on a master
write cycle, or that the target device has presented
valid data onto the bus during master read cycles.
Input/Output
Output
Input/Output
LB/VESA
VLBEN
JTAGSEL
Mode Selected
0
X*
0
VL Bus mode with 4 interrupts and daisy chain arbitration
0
X*
1
VL Bus mode with 2 interrupts and JTAG
1
0
0
VL Bus mode with 4 interrupts and daisy chain arbitration
1
0
1
VL Bus mode with 2 interrupts and JTAG
1
1
X
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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