
Am79C965A
147
A value of zero will in the DMABAT
register with the TIMER bit in CSR4
set to ONE will produce single linear
burst sequences per bus master
period when programmed for linear
burst mode, and will yield sets of
three transfers when not pro-
grammed for linear burst mode.
The Bus Activity Timer is set to a
value of 00h after H_RESET or
S_RESET and is unaffected by
STOP.
Read/write accessible only when
STOP bit is set.
CSR84: DMA Address Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
DMABA
DMA Address Register.
This register contains the lower 16
bits of the address of system
memory for the current DMA cycle.
The Bus Interface Unit controls the
Address Register by issuing
increment commands to increment
the memory address for sequential
operations. The DMABA register is
undefined until the first PCnet-32
controller DMA operation. When the
ENTST bit in CSR4 is set, all writes
to this register will automatically
perform an increment cycle.
Read/write accessible only when
STOP bit is set.
CSR85: DMA Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
DMABA
DMA Address Register.
This register contains the upper 16
bits of the address of system
memory for the current DMA cycle.
The Bus Interface Unit controls the
Address Register by issuing
increment commands to increment
the memory address for sequential
operations. The DMABA register is
undefined until the first PCnet-32
controller DMA operation. When the
ENTST bit in CSR4 is set, all writes
to this register will automatically
perform an increment cycle.
Read/write accessible only when
STOP bit is set.
CSR86: Buffer Byte Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved, Read and written with
ones.
11-0
DMABC
DMA Byte Count Register. Con-
tains a Two
’
s complement binary
number of the current size of the
remaining transmit or receive buffer
in bytes. This register is
incremented by the Bus Interface
Unit. The DMABC register is
undefined until written. When
ENTST (CSR4.15) is asserted, all
writes to this register will
automatically perform an increment
cycle.
Read/write accessible only when
STOP bit is set.
CSR88: Chip ID Lower
Bit
Name
Description
This register is exactly the same as
the Chip ID register in the JTAG
description.
31 - 28 Version. This 4-bit pattern is silicon-revision
dependent.
27 - 12 Part number. The 16-bit code for the PCnet-32
controller is 0010 0100 0011 0000b.
11 - 1
Manufacturer
manufacturer code for AMD is
00000000001b. This code is per the
JEDEC Publication 106-A.
ID.
The
11-bit
0
Always a logic 1.
CSR89: Chip ID Upper
Bit
Name
Description
The lower 16 bits of this register are
exactly the same as the upper 16
bits of the Chip ID register in the
JTAG description, which are exactly
the same as the upper 16 bits of
CSR88.
31 - 16
Reserved
undefined.
locations.
Read
as
15 - 12
Version. This 4-bit pattern is silicon-
revision dependent.