參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 133/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
133
Read/write accessible only when
STOP bit is set. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
CSR9: Logical Address Filter, LADRF[31:16]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 LADRF[31:16] Logical
Address
Filter,
LADRF[31:16]. Defined only after
the initialization block has been
successfully read or a direct I/O
write has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
CSR10: Logical Address Filter, LADRF[47:32]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 LADRF[47:32] Logical
Address
Filter,
LADRF[47:32]. Defined only after
the initialization block has been
successfully read or a direct I/O
write has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
CSR11: Logical Address Filter, LADRF[63:48]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
LADRF[63:48] Logical
LADRF[63:48]. Defined only after
the initialization block has been
successfully read or a direct I/O
write has been performed on this
register.
Address
Filter,
Read/write accessible only when
STOP bit is set. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
CSR12: Physical Address Register, PADR[15:0]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 PADR[15:0] Physical
Address
Register,
PADR[15:0]. Defined only after the
initialization block has been
successfully read or a direct I/O
write has been performed on this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only when
STOP bit is set. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
CSR13: Physical Address Register, PADR[31:16]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 PADR[31:16]Physical
Address
Register,
PADR[31:16]. Defined only after the
initialization block has been
successfully read or a direct I/O
write has been performed on this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only when
STOP bit is set. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
CSR14: Physical Address Register, PADR[47:32]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PADR[47:32]Physical
PADR[47:32]. Defined only after the
initialization block has been
successfully read or a direct I/O
write has been performed on this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Address
Register,
Read/write accessible only when
STOP bit is set. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
相關(guān)PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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