42
Am79C965A
Microwire EEPROM Interface
EESK
EEPROM Serial Clock
The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the microwire interface protocol. EESK is con-
nected to the microwire EEPROM
’
s Clock pin. It is con-
trolled by either the PCnet-32 controller directly during
a read of the entire EEPROM, or indirectly by the host
system by writing to BCR19, bit 1.
Output
EESK can be used during programming of
external
EEPROM-programmable registers
that do not use the
microwire protocol as follows:
When the PCnet-32 controller is performing a serial
read of the IEEE Address EEPROM through the
microwire interface, the SHFBUSY signal will serve as
a serial shift enable to allow the EEPROM data to be
serially shifted into an external device or series of de-
vices. This same signal can be used to gate the
output
of the programmed logic to avoid the problem of
releasing intermediate values to the rest of the system
board logic. The EESK signal can serve as the clock,
and EEDO will serve as the input data stream to the
programmable shift register.
EEDO
EEPROM Data Out
The EEDO signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the microwire interface protocol. EEDO is con-
nected to the microwire EEPROM
’
s Data Output pin. It
is controlled by the EEPROM during reads. It may be
read by the host system by reading BCR19, bit 0.
Input
EEDO can be used during programming of
external
EEPROM-programmable registers
that do not use the
microwire protocol as follows:
When the PCnet-32 controller is performing a serial
read of the IEEE Address EEPROM through the
microwire interface, the SHFBUSY signal will serve as
a serial shift enable to allow the EEPROM data to be
serially shifted into an external device or series of de-
vices. This same signal can be used to gate the
output
of the programmed logic to avoid the problem of
releasing intermediate values to the rest of the system
board logic. The EESK signal can serve as the clock,
and EEDO will serve as the input data stream to the
programmable shift register.
EECS
EEPROM Chip Select
The function of the EECS signal is to indicate to the
microwire EEPROM device that it is being accessed.
Output
The EECS signal is active high. It is controlled by either
the PCnet-32 controller during a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
EEDI
EEPROM Data In
The EEDI signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. EEDI
functions as an output. This pin is designed to directly
interface to a serial EEPROM that uses the microwire
interface protocol. EEDI is connected to the microwire
EEPROM
’
s Data Input pin. It is controlled by either the
PCnet-32 controller during command portions of a read
of the entire EEPROM, or indirectly by the host system
by writing to BCR19, bit 0.
Attachment Unit Interface
C
I±
Collision In
A differential input pair signaling the PCnet-32
controller that a collision has been detected on the
network media, indicated by the CI± inputs being
driven with a 10 MHz pattern of sufficient amplitude
and pulse width to meet ISO 8802-3 (IEEE/ANSI
802.3) standards. Operates at pseudo ECL levels.
DI±
Data In
A differential input pair to the PCnet-32 controller
carrying Manchester encoded data from the network.
Operates at pseudo ECL levels.
DO±
Output
Input
Input
Data Out Output
A differential output pair from the PCnet-32 controller
for transmitting Manchester encoded data to the
network. Operates at pseudo ECL levels.
Twisted Pair Interface
RXD±
10BASE-T Receive Data
10BASE-T port differential receivers.
TXD±
10BASE-T Transmit Data
10BASE-T port differential drivers.
TXP±
10BASE-T Pre-distortion Control
These outputs provide transmit predistortion control in
conjunction with the 10BASE-T port differential drivers.
Input
Output
Output