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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 76/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
Effect of AHOLD
Assertion of AHOLD during Linear Burst transfers will
cause the PCnet-32 controller to float some portion of
the address bus beginning at the next clock cycle. If
BRDY is returned while AHOLD is active, then the
linear burst sequence will continue until the current
burst would otherwise normally terminate, since the
data bus and the lower portion of the address bus may
remain active during AHOLD. However, a new linear
burst sequence, requiring a new ADS assertion, will not
be started while AHOLD is active.
When AHOLD is asserted during T1 of a linear burst,
then the linear burst operation will be suspended until
AHOLD is de-asserted. Once AHOLD is de-asserted,
then the PCnet-32 controller will start the suspended
linear burst with the intended address. See Figure 23.
(Note that the intended T1 of the linear burst sequence
has been labeled Ta in the figure, since a T1 was never
executed due to the suspension of the address bus re-
quired by the assertion of AHOLD.)
When AHOLD is asserted in the middle of a linear
burst, the linear burst may proceed without stalling or
halting. AHOLD requires that PCnet-32 controller float
a portion of its address bus, but linear burst data cycles
will still proceed, since the AHOLD signal only affects a
portion of the address bus, and that portion of the
address bus is not being used for the middle accesses
of a linear burst.
However, if AHOLD is asserted in the middle of a linear
burst operation, and the AHOLD signal is held long
enough that a new linear burst sequence will start (a
new ADS is to be issued by the PCnet-32 controller)
then at the end of the current linear sequence, the
PCnet-32 controller must wait for the AHOLD signal to
become inactive before beginning the next linear se-
quence, since the AHOLD signal would now interfere
with the PCnet-32 controller
’
s wish to assert ADS and
a new address on the entire address bus. During the
time that the PCnet-32 controller is waiting for the
release of
the AHOLD signal, the PCnet-32 controller will
continue
to drive the command signals, but ADS will be
driven inactive.
Note that if RDYRTN is asserted during a linear burst
sequence while AHOLD is active, then no more access
will be performed until AHOLD is de-asserted. This is
because the assertion of RDYRTN will cause the
PCnet-32 controller to insert a new T1 cycle into the lin-
ear burst. A T1 cycle requires assertion of ADS, but
ADS assertion is not allowed as long as AHOLD is still
asserted. Therefore, the T1 cycle is delayed until the
AHOLD is de-asserted.
The portion of the Address Bus that will be floated at
the time of an address hold operation will be
determined by the value of the Cache Line Length
register (BCR18, bits 15
–
11). Table 23 lists all of the
legal values of CLL showing the portion of the Address
Bus that will become floated during an address hold
operation.
Table 23. CLL Value of Floated Address in AHOLD
Note that the default value of CLL after H_RESET is
00100. All timing diagrams in this document are drawn
with the assumption that this is the value of CLL.
CLL Value
Floated Portion of Address
Bus During AHOLD
00000
None
00001
A31
–
A2
00010
A31
–
A3
00011
Reserved CLL Value
00100
A31
–
A4
00101
–
00111
Reserved CLL Values
01000
A31
–
A5
01001
–
01111
Reserved CLL Values
10000
A31
–
A6
10001
–
11111
Reserved CLL Values
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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