參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 130/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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130
Am79C965A
Read/Write accessible always. The
LAPPEN bit will be reset to ZERO by
H_RESET or S_RESET and will be
unaffected by STOP.
See Appendix D for more infor-
mation on the LAPP concept.
4
DXMT2PD Disable Transmit Two Part Deferral.
If DXMT2PD is set, Transmit Two
Part Deferral will be disabled.
Read/Write
DXMT2PD is cleared by H_RESET
or S_RESET and is not affected by
STOP.
accessible
always.
3
EMBA
Enable Modified Back-off Algo-
rithm. If EMBA is set, a modified
back-off algorithm is implemented.
Read/Write
EMBA is cleared by H_RESET or
S_RESET and is not affected by
STOP.
accessible
always.
2
BSWP
Byte Swap. This bit is used to
choose between big and little
Endian modes of operation. When
BSWP is set to a ONE, big Endian
mode is selected. When BSWP is
set to ZERO, little Endian mode is
selected.
When big Endian mode is selected,
the PCnet-32 controller will swap the
order of bytes on the data bus during
FIFO transfers only. Specifically,
D31
–
24 becomes Byte0, D23
–
16
becomes Byte1, D15
–
8 becomes
Byte2 and D7
–
0 becomes Byte3
when big Endian mode is selected.
When little Endian mode is selected,
the order of bytes on the data bus is:
D31
–
24 is Byte3,
D23
–
16 is Byte2,
D15
–
8 is Byte1
and D7
–
0 is Byte0.
Byte swap only affects data transfers
that involve the FIFOs. Initialization
block transfers are not affected by
the setting of the BSWP bit.
Descriptor transfers are not affected
by the setting of the BSWP bit. RDP,
RAP and BDP accesses are not
affected by the setting of the BSWP
bit. APROM transfers are not af-
fected by the setting of the BSWP
bit.
BSWP is write/readable regardless
of the state of the STOP bit. BSWP
is cleared by H_RESET or
S_RESET and is not affected by
STOP.
1-0
RES
Reserved locations. The default
value is ZERO for both locations.
Writing a ONE to these bits has no
effect on device function; if a ONE is
written to these bits, then a ONE will
be read back. Existing drivers may
write a ONE to these bits for
compatibility, but new drivers should
write a ZERO to these bits and
should treat the read value as
undefined.
CSR4: Test and Features Control
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
ENTST
Enable Test Mode operation. Setting
ENTST to ONE enables internal test
functions which are useful only for
stand alone integrated circuit
testing. In addition, the Runt Packet
Accept (RPA) bit (CSR124, bit 3)
may be changed only when ENTST
is set to ONE.
To enable RPA, the user must first
write a ONE to the ENTST bit. Next,
the user must first write a ONE to the
RPA bit (CSR124, bit 3). Finally, the
user must write a ZERO to the
ENTST bit to take the device out of
test mode operation. Once the RPA
bit has been set to ONE, the device
will remain in the Runt Packet
Accept mode until the RPA bit is
cleared to ZERO.
Read/Write accessible. ENTST is
cleared by H_RESET or S_RESET
and is unaffected by the STOP bit.
14 DMAPLUS
When DMAPLUS =
“
1
”
, disables the
burst transaction counter, CSR80. If
DMAPLUS =
“
0
”
, the burst
transaction counter is enabled.
Read
DMAPLUS is cleared by H_RESET
or S_RESET and is unaffected by
the STOP bit.
and
Write
accessible.
13
TIMER
Timer Enable Register. If TIMER is
set, the Bus Activity Timer Register,
CSR82 is enabled. If TIMER is
cleared, the Bus Activity Timer
Register is disabled.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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