參數(shù)資料
型號(hào): Am79C965A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述: PCnet?-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù): 175/228頁(yè)
文件大?。?/td> 1681K
代理商: AM79C965A
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Am79C965A
175
23-16 RPC
Runt Packet Count. Indicates the
accumulated number of runts that
were addressed to this node since
the last time that a receive packet
was successfully received and its
corresponding RMD2 ring entry
was written to by the PCnet-32
controller. In order to be included in
the RPC value, a runt must be long
enough to meet the minimum
requirement of the internal address
matching logic. The minimum
requirement for a runt to pass the
internal address matching
mechanism is: 18 bits of valid
preamble plus a valid SFD
detected, followed by 7 bytes of
frame data. This requirement is
unvarying, regardless of the
address matching mechanisms in
force at the time of reception (i.e.
physical, logical, broadcast or
promiscuous). The PCnet-32
controller implementation of this
counter may not be compatible
with the ILACC RPC definition.
15-12 ZEROs
This field is reserved. PCnet-32
controller will write ZEROs to these
locations.
11-0
MCNT
MESSAGE Byte COUNT is the
length in bytes of the received
message, expressed as an un-
signed binary integer. MCNT is
valid only when ERR is clear and
ENP is set. MCNT is written by the
PCnet-32 controller and cleared by
the host.
RMD3
Bit
Name
Description
31-0
RES
Reserved locations. All bits must
be ZEROs.
Transmit Descriptors
When SSIZE32 = 0 (BCR 20[8]), then the software
structures are defined to be 16 bits wide, and transmit
descriptors look as shown in Table 61.
PCnet-32 reference names within the table above refer
to the descriptor definitions given in text below. Since
the text descriptions are for 32-bit descriptors, the table
above shows the mapping of the 32-bit descriptors into
the 16-bit descriptor space. Since 16-bit descriptors
are a subset of the 32-bit descriptors, some portions of
the 32-bit descriptors may not appear in Table 61.
When SSIZE32 = 1 (BCR 20[8]), then the software
structures are defined to be 32 bits wide, and transmit
descriptors look as shown in Table 62.
Table 61. Transmit Descriptor (SSIZE32 = 0)
Table 62. Transmit Descriptor (SSIZE32 = 1)
* NA = These 8 bits do not exist in any LANCE descriptor
.
The Transmit Descriptor Ring Entries (TDREs) are
composed of 4 transmit message descriptors (TMD0-
TMD3). Together they contain the following
information:
I
The address of the actual message data buffer in
user or host memory.
I
The length of the message buffer.
I
Status information indicating the condition of the
buffer. The eight most significant bits of TMD1
(TMD1[31:24]) are collectively termed the STATUS
of the transmit descriptor.
LANCE
Descriptor
Designation
PCnet-32
Descriptor Designation
Address
Bits 15-0
Bits 15-8
Bits 7-0
CRDA+00
TMD0
TMD0[15:0]
CRDA+02
TMD1
TMD1[31:24]
TMD0[23:16]
CRDA+04
TMD2
TMD1[15:0]
CRDA+06
TMD3
TMD2[15:0]
LANCE
Descriptor Designation
PCnet-32 Descriptor
Designation
Address
Bits 31-24
Bits 23-16
Bits 15-8
Bits 7-0
Bits 31-0
CTDA+00
*NA
TMD1[7:0]
TMD0[15:8]
TMD0[7:0]
TMD0
CTDA+04
TMD1[15:8]
*NA
TMD2[15:8]
TMD2[7:0]
TMD1
CTDA+08
TMD3[15:8]
TMD3[7:0]
*NA
*NA
TMD2
CTDA+0C
*NA
*NA
*NA
*NA
TMD3
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