參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 177/228頁
文件大小： 1681K
代理商： AM79C965A
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Am79C965A
177
and there is no data chaining. ENP
is set by the host and unchanged
by the PCnet-32 controller.
23-16 RES
Reserved locations.
15-12 ONES
Must be Ones. This field is written
by the host and unchanged by the
PCnet-32 controller.
11-0
BCNT
BUFFER BYTE COUNT is the
usable length of the buffer pointed
to by this descriptor, expressed as
the two
’
s complement of the length
of the buffer. This is the number of
bytes from this buffer that will be
transmitted by the PCnet-32
controller. This field is written by
the host and unchanged by the
PCnet-32 controller. There are no
minimum buffer size restrictions.
TMD2
Bit
Name
Description
31
BUFF
BUFFER ERROR is set by the
PCnet-32 controller during
transmission when the PCnet-32
controller does not find the ENP
flag in the current buffer and does
not own the next buffer. This can
occur in either of two ways:
1. The OWN bit of the next buffer
is zero.
2. FIFO underflow occurred before
the PCnet-32 controller
obtained the STATUS byte
(TMD1[31:24]) of the next
descriptor. BUFF is set by the
PCnet-32 controller and cleared
by the host. BUFF error will turn
off the transmitter (CSR0,
TXON = 0).
If a Buffer Error occurs, an Un-
derflow Error will also occur. BUFF
is not valid when LCOL or RTRY
error is set during transmit data
chaining. BUFF is set by the
PCnet-32 controller and cleared by
the host.
30
UFLO
UNDERFLOW ERROR indicates
that the transmitter has truncated a
message due to data late from
memory. UFLO indicates that the
FIFO has emptied before the end
of the frame was reached. Upon
UFLO error, the transmitter is
turned off (CSR0, TXON = 0).
UFLO is set by the PCnet-32
controller and cleared by the host.
29
EXDEF
EXCESSIVE DEFERRAL. Indi-
cates that the transmitter has
experienced Excessive Deferral on
this transmit frame, where
Excessive Deferral is defined in
ISO 8802-3 (IEEE/ANSI 802.3).
28
LCOL LATE COLLISION
collision has occurred after the slot
time of the channel has elapsed.
The PCnet-32 controller does not
retry on late collisions. LCOL is set
by the PCnet-32 controller and
cleared by the host.
indicates
that
a
27
LCAR
LOSS OF CARRIER is set in AUI
mode when the carrier is lost
during an PCnet-32 controller-
initiated transmission. The
PCnet-32 controller does not re-try
upon loss of carrier. It will continue
to transmit the whole frame until
done. In 10BASE-T mode LCAR
will be set when the T-MAU is in
Link Fail state. LCAR is not valid in
Internal Loopback Mode. LCAR is
set by the PCnet-32 controller and
cleared by the host.
26
RTRY
RETRY ERROR indicates that the
transmitter has failed after 16
attempts to successfully transmit a
message, due to repeated
collisions on the medium. If DRTY
= 1 in the MODE register, RTRY
will set after 1 failed transmission
attempt. RTRY is set by the
PCnet-32 controller and cleared by
the host.
25-16 TDR
TIME
TOMETRY reflects the state of an
internal PCnet-32 controller
counter that counts at a 10 MHz
rate from the start of a transmis-
sion to the occurrence of a colli-
sion or loss of carrier. This value is
useful in determining the ap-
proximate distance to a cable fault.
The TDR value is written by the
PCnet-32 controller and is valid
only if RTRY is set.
DOMAIN
REFLEC-
Note that 10 MHz gives very low
resolution and in general has not
been found to be particularly
useful. This feature is here
primarily to maintain full
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