參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 176/228頁(yè)
文件大小： 1681K
代理商： AM79C965A
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176
Am79C965A
TMD0
Bit
Name
Description
31-0
TBADR
Transmit Buffer address. This field
contains the address of the
transmit buffer that is associated
with this descriptor.
TMD1
Bit
Name
Description
31
OWN
This bit indicates that the de-
scriptor entry is owned by the host
(OWN=0) or by the PCnet-32
controller (OWN=1). The host sets
the OWN bit after filling the buffer
pointed to by the descriptor entry.
The PCnet-32 controller clears the
OWN bit after transmitting the
contents of the buffer. Both the
PCnet-32 controller and the host
must not alter a descriptor entry
after it has relinquished ownership.
30
ERR
ER is the OR of UFLO, LCOL,
LCAR, or RTRY. ERR is set by the
PCnet-32 controller and cleared by
the host. This bit is set in the
current descriptor when the error
occurs, and therefore may be set in
any descriptor of a chained buffer
transmission.
29
ADD_FCS/NO_FCS
Bit 29 functions as ADD_FCS
when programmed for the default
I/O style of PCnet-ISA and when
programmed for the I/O style
PCnet-32 controller. Bit 29
functions as NO_FCS when
programmed for the I/O style
ILACC.
ADD_FCS ADD_FCS dynamically controls
the generation of FCS on a frame
by frame basis. It is valid only if the
STP bit is set. When ADD_FCS is
set, the state of DXMTFCS is
ignored and transmitter FCS
generation is activated. When
ADD_FCS = 0, FCS generation is
controlled
ADD_FCS is set by the host, and
unchanged by the PCnet-32
controller. This was a reserved bit
in the LANCE (Am7990).
This
function differs from the ILACC
function for this bit.
by
DXMTFCS.
NO_FCS
NO_FCS dynamically controls the
generation of FCS on a frame by
frame basis. It is valid only if the
ENP bit is set. When NO_FCS is
set, the state of DXMTFCS is
ignored and transmitter FCS
generation is deactivated. When
NO_FCS = 0, FCS generation is
controlled by DXMTFCS. NO_FCS
is set by the host, and unchanged
by the PCnet-32 controller. This
was a reserved bit in the LANCE
(Am7990).
This function is identi
cal to the ILACC function for this
bit.
28
MORE
MORE indicates that more than
one retry was needed to transmit a
frame. The value of MORE is
written by the PCnet-32 controller.
This bit has meaning only if the
ENP bit is set.
27
ONE
ONE indicates that exactly one
retry was needed to transmit a
frame. ONE flag is not valid when
LCOL is set. The value of the ONE
bit is written by the PCnet-32
controller. This bit has meaning
only if the ENP bit is set.
26
DEF
DEFERED indicates that the
PCnet-32 controller had to defer
while trying to transmit a frame.
This condition occurs if the channel
is busy when the PCnet-32
controller is ready to transmit. DEF
is set by the PCnet-32 controller
and cleared by the host.
25
STP
START OF PACKET indicates that
this is the first buffer to be used by
the PCnet-32 controller for this
frame. It is used for data chaining
buffers. The STP bit must be set in
the first buffer of the frame, or the
PCnet-32 controller will skip over
the descriptor and poll the next
descriptor(s) until the OWN and
STP bits are set.
STP is set by the host and un-
changed by the PCnet-32
controller.
24
ENP
END OF PACKET indicates that
this is the last buffer to be used by
the PCnet-32 controller for this
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
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