參數(shù)資料
型號(hào): Am79C965A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述: PCnet?-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù): 2/228頁(yè)
文件大?。?/td> 1681K
代理商: AM79C965A
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2
Am79C965A
The PCnet-32 controller is a complete Ethernet node
integrated into a single VLSI device. It contains a bus
interface unit, a DMA buffer management unit, an ISO
8802-3 (IEEE/ANSI 802.3)-defined media access con-
trol (MAC) function, individual 136-byte transmit and
128-byte receive FIFOs, an ISO 8802-3 (IEEE/ANSI
802.3)-defined attachment unit interface (AUI) and
twisted-pair transceiver medium attachment unit
(10BASE-T MAU), and a microwire EEPROM interface.
The PCnet-32 controller is also register-compatible
with the LANCE (Am7990) Ethernet controller, the C-
LANCE (Am79C90) Ethernet controller, the ILACC
(Am79C900) Ethernet controller, and all Ethernet
controllers in the PCnet family, including the PCnet-ISA
controller (Am79C960), the PCnet-ISA+ controller
(Am79C961), PCnet-ISA II (Am79C961A), and the
PCnet-PCI II controller (Am79C970A). The buffer man-
agement unit supports the LANCE, ILACC
(Am79C900), and PCnet descriptor software models.
The PCnet-32 controller is software-compatible with
Novell NE2100 and NE1500 Ethernet adapter card ar-
chitectures. In addition, a Sleep function has been in-
corporated to provide low standby current, which is
essential for notebooks and Green PCs.
The 32-bit demultiplexed bus interface unit provides a
direct interface to the VESA VL-Bus and 486 series
microprocessors, simplifying the design of an Ethernet
node in a PC system. With its built-in support for both
little and big endian byte alignment, this controller also
addresses proprietary non-PC applications.
Key PCnet-32 configuration parameters, including the
unique IEEE physical address, can be read from an ex-
ternal non-volatile memory (serial EEPROM) immedi-
ately following system reset. In addition, the I/O
location at which the internal registers are accessed
may be stored in the EEPROM, allowing the software
model of the device to be located appropriately in
system I/O space during system initialization.
The controller has the capability to select automatically
either the AUI port or the twisted-pair transceiver. Only
one interface is active at any one time. The individual
transmit and receive FIFOs reduce system overhead,
providing sufficient latency during frame transmission
and reception, and minimizing intervention during
normal network error recovery. The integrated
Manchester encoder/decoder (MENDEC) eliminates
the need for an external serial interface adapter (SIA)
in the node system. The built-in general purpose serial
interface (GPSI) allows the MENDEC to be bypassed.
In addition, the device provides programmable on-chip
LED drivers for transmit, receive, collision, receive
polarity, link integrity, or jabber status. The PCnet-32
controller also provides an external address detection
interface (EADI) to allow external hardware address
filterin
g in
inter-networking applications.
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