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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 132/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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132
Am79C965A
will set the value of this bit to a
ZERO.
3
TXSTRT Transmit
Start
status
is
set
whenever PCnet-32 controller
begins transmission of a frame.
When TXSTRT is set, INTR is
asserted if IENA = 1 and the mask
bit TXSTRTM (CSR4 bit 2) is
cleared.
TXSTRT is set by the MAC Unit and
cleared by writing a
“
1
”
, by
H_RESET or S_RESET, or setting
the STOP bit. Writing a
“
0
”
has no
effect.
2
TXSTRTM Transmit Start Mask. If TXSTRTM is
set, the TXSTRT bit in CSR4 will be
masked and unable to set INTR flag
in CSR0.
Read/Write accessible. TXSTRTM
is set to a ONE by H_RESET or
S_RESET and is not affected by the
STOP bit.
1
JAB
Jabber Error is set when the
PCnet-32 controller Twisted-pair
MAU function exceeds an allowed
transmission limit. Jabber is set by
the T-MAU cell and can only be
asserted in 10BASE-T mode.
When JAB is set, INTR is asserted if
IENA = 1 and the mask bit JABM
(CSR4[0]) is cleared.
JAB is set by the T-MAU circuit and
cleared by writing a
“
1
”
. Writing a
“
0
”
has no effect. JAB is also cleared by
H_RESET or S_RESET or setting
the STOP bit.
When
(BCR20[7:0]) has been pro-
grammed to the ILACC compati-
bility mode, then this bit has no
meaning and PCnet-32 controller
will never set the value of this bit to
ONE.
the
SWSTYLE
register
0
JABM
Jabber Error Mask. If JABM is set,
the JAB bit in CSR4 will be masked
and unable to set INTR flag in
CSR0.
Read/Write accessible. JABM is set
to a ONE by H_RESET or
S_RESET and is not affected by
STOP.
When
(BCR20[7:0]) has been pro-
grammed to the ILACC compati-
bility mode, then this bit has no
meaning and PCnet-32 controller
will set the value of this bit to a
ZERO.
the
SWSTYLE
register
CSR6: RX/TX Descriptor Table Length
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 TLEN
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during PCnet-32 controller
initialization. This field is written
during the PCnet-32 controller
initialization routine.
Read accessible only when STOP
bit is set. Write operations have no
effect and should not be performed.
TLEN is only defined after
initialization. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
11-8
RLEN
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block during
PCnet-32 controller initialization.
This field is written during the
PCnet-32 controller initialization
routine.
Read accessible only when STOP
bit is set. Write operations have no
effect and should not be performed.
RLEN is only defined after
initialization. These bits are
unaffected by H_RESET, S_RESET,
or STOP.
7-0
RES
Reserved locations. Read as zero.
Write operations should not be
performed.
CSR8: Logical Address Filter, LADRF[15:0]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 LADRF[15:0] Logical
Address
Filter,
LADRF[15:0]. Defined only after the
initialization block has been
successfully read or a direct I/O
write has been performed on this
register.
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PDF描述 |
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| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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