參數(shù)資料
型號(hào)： Am79C965A
廠(chǎng)商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 21/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
21
LOW value means that an EEPROM is not present, and
EEDET will be set to ZERO. See the
“
EEPROM Auto-
detection
”
section for more details.
If no LED circuit is to be attached to this pin, then a pull-
up or pull-down resistor must be attached instead, in
order to resolve the EEDET setting.
LED2
LED2
This pin is shared with the SRDCLK function. When
operating as LED2, the function and polarity on this pin
are programmable through BCR6. The LED2 output
from the PCnet-32 controller is capable of sinking the
necessary 12 mA of current to drive an LED directly.
Output
This pin also selects address width for Software
Relocatable Mode. When this pin is HIGH during
Software Relocatable Mode, then the device will be
programmed to use 32 bits of addressing while
snooping accesses on the bus during Software
Relocatable Mode. When this pin is LOW during
Software Relocatable Mode, then the device will be
programmed to use 24 bits of addressing while
snooping accesses on the bus during Software
Relocatable Mode. The upper 8 bits of address will be
assumed to match during the snooping operation when
LED2 is LOW. The 24-bit addressing mode is intended
for use in systems that employ the GPSI signals. For
more information on the GPSI function see section
General Purpose Serial Interface
.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in
order to resolve the Software Relocatable Mode ad-
dress width setting.
LEDPRE3
LEDPRE3
This pin is shared with the EEDO function. When
operating as LEDPRE3, the function and polarity on
this pin are programmable through BCR7. This signal
is labeled as LED
“
PRE
”
3 because of the multi-
function nature of this pin. If an LED circuit were directly
attached to this
pin, it would create an
I
OL
requirement that
could not be
met by the serial EEPROM that would also
be attached to this pin. Therefore, if this pin is to be
used as an additional LED output while an EEPROM is
used in the system, then buffering is required between
the LEDPRE3 pin and the LED circuit. If no EEPROM
is included in the system design, then the LEDPRE3
signal may be directly connected to an LED without
buffering. The LEDPRE3 output from the PCnet-32
controller is capable of sinking the necessary 12 mA of
current to drive an LED in this case. For more details
regarding LED connection, see the section on LEDs.
Output
LNKST
Link Status
This pin provides 12 mA for driving an LED. It indicates
an active link connection on the 10BASE-T interface.
The function and polarity are programmable through
BCR4. Note that this pin is multiplexed with the EEDI
function.
Output
This pin remains active in snooze mode.
SHFBUSY
Shift Busy
The function of the SHFBUSY signal is to indicate
when the last byte of the EEPROM contents has been
shifted out of the EEPROM on the EEDO signal line.
This information is useful for
external EEPROM-
programmable registers
that do not use the microwire
protocol, as is described herein: When the PCnet-32
controller is performing a serial read of the EEPROM
through the microwire interface, the SHFBUSY signal
will be driven HIGH. SHFBUSY can serve as a serial
shift enable to allow the EEPROM data to be serially
shifted into an external device or series of devices. The
SHFBUSY signal will remain actively driven HIGH until
the end of the EEPROM read operation. If the
EEPROM checksum was verified, then the SHFBUSY
signal will be driven LOW at the end of the EEPROM
read operation. If the EEPROM checksum verification
failed, then the SHFBUSY signal will remain HIGH.
This function effectively demarcates the end of a
successful EEPROM read operation and therefore is
useful as a programmable-logic
low-active output
enable
signal. For more details on external EEPROM-
programmable registers, see the EEPROM
Microwire
Access
section under Hardware Access.
Output
This pin can be controlled by the host system by writing
to BCR19, bit 3 (EBUSY).
SLEEP
Sleep
When SLEEP input is asserted (active LOW), the
PCnet-32 controller performs an internal system reset
of the S_RESET type and then proceeds into a power
savings mode. (The reset operation caused by SLEEP
assertion will not affect BCR registers.) All outputs will
be placed in their normal S_RESET condition. During
sleep mode, all PCnet-32 controller inputs will be ig-
nored except for the SLEEP pin itself. De-assertion of
SLEEP results in wake-up. The system must refrain
from starting the network operations of the PCnet-32
controller for 0.5 seconds following the de-assertion of
the SLEEP signal in order to allow internal analog cir-
cuits to stabilize.
Input
Both LCLK and XTAL1 inputs must have valid clock
signals present in order for the SLEEP command to
take effect.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
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AM79C970A 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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