參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 166/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
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166
Am79C965A
accesses to these locations may
change the PCnet-32 controller
register contents, but the EEPROM
locations will not be affected.
EEPROM locations may be
accessed directly through BCR19.
At the end of the read operation, the
PREAD bit will automatically be
reset to a ZERO by the PCnet-32
controller and PVALID will bet set,
provided that an EEPROM existed
on the microwire interface pins and
that the checksum for the entire 36
bytes of EEPROM was correct.
Note that when PREAD is set to a
ONE, then the PCnet-32 controller
will no longer respond to I/O
accesses directed toward it, until the
PREAD operation has completed
successfully.
If a PREAD command is given to the
PCnet-32 controller but no
EEPROM is attached to the
microwire interface pins, then the
PREAD command will terminate
early, the PREAD bit will be cleared
to a ZERO and the PVALID bit will
remain reset with a value of ZERO.
The PCnet-32 controller will then
enter Software Relocatable Mode to
await further programming. This ap-
plies to the automatic read of the
EEPROM after H_RESET as well as
to host initiated PREAD commands.
EEPROM programmable locations
on board the PCnet-32 controller will
be set to their default values by such
an aborted PREAD operation. For
example, if the aborted PREAD
operation immediately followed the
H_RESET operation, then the final
state
of
the
programmable locations will be
equal
to
the
programming for those locations.
EEPROM
H_RESET
If a PREAD command is given to the
PCnet-32 controller and the
autodetection pin (EESK/LED1/
SFBD) indicates that no EEPROM is
present, then the EEPROM read
operation will still be attempted.
Note that at the end of the
H_RESET operation, a read of the
EEPROM will be performed
automatically. This H_RESET-
generated EEPROM read function
will not proceed if the auto-detection
pin (EESK/LED1/SFBD) indicates
that no EEPROM is present.
Instead, Software Relocatable Mode
will be entered immediately.
PREAD is set to ZERO during
H_RESET and is unaffected by
S_RESET or STOP.
PREAD is only writable when the
STOP bit is set to ONE.
13
EEDET
EEPROM Detect. This bit indicates
the sampled value of the EESK/
LED1/SFBD pin at the end of
H_RESET. The value of this bit is
independent whether or not an
EEPROM is actually present at the
EEPROM interface. It is only a
function of the sampled value of the
EESK/LEDI/SFBD pin at the end of
H_RESET.
The value of this bit is determined at
the end of the H_RESET operation.
It is unaffected by S_RESET or
STOP.
This bit is not writable. It is read only.
Table 51 indicates the possible
combinations of EEDET and the
existence of an EEPROM and the
resulting operations that are
possible on the EEPROM microwire
interface.
12-5
RES
Reserved locations. Written as
ZERO, read as undefined.
4
EEN
EEPROM port enable. When this bit
is set to a one, it causes the values
of EBUSY, ECS, ESK and EDI to be
driven onto the SHFBUSY, EECS,
EESK and EEDI pins, respectively.
When this bit is reset to a zero, then
the SHFBUSY pin will be driven with
the inverse of the PVALID (bit 15 of
BCR19) value. PVALID is set to
“
ONE
”
if the EEPROM read was
successful. It is set to
“
ZERO
”
otherwise.
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