- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > Am79C965A (Advanced Micro Devices, Inc.) PCnet?-32 Single-Chip 32-Bit Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 94/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁當前第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁
94
Am79C965A
is detected within the 4.0 μs
–
6.0 μs IFS1 period, but
will commence timing of the entire IFS1 period.
Contention Resolution (Collision Handling)
Collision detection is performed and reported to the
MAC engine by the integrated Manchester Encoder/
Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits
being transmitted, the MAC Engine will abort the
transmission, and append the jam sequence
immediately. The jam sequence is a 32-bit all zeroes
pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to
normal collisions (those within the slot time). Detection
of collision will cause the transmission to be
rescheduled, dependent on the back-off time that the
MAC Engine computes. If a single retry was required,
the ONE bit will be set in the Transmit Frame Status. If
more than one retry was required, the MORE bit will be
set. If all 16 attempts experienced collisions, the RTRY
bit will be set (ONE and MORE will be clear), and the
transmit message will be flushed from the FIFO. If
retries have been disabled by setting the DRTY bit in
CSR15, the MAC Engine will abandon transmission of
the frame on detection of the first collision. In this case,
only the RTRY bit will be set and the transmit message
will be flushed from the FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the
jam sequence and set the LCOL bit. No retry attempt
will be scheduled on detection of a late collision, and
the transmit message will be flushed from the FIFO.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a
“
truncated binary exponential back-off
”
algo-
rithm which provides a controlled pseudo random
mechanism to enforce the collision back-off interval,
be-fore retransmission is attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“
At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to re-
transmit the frame. The delay is an integer multiple
of slotTime. The number of slot times to delay
before the nth retransmission attempt is chosen as
a uniformly distributed random integer r in the
range:
0
￡
r < 2k
–
1
where k = min (n,10).
”
The PCnet-32 controller provides an alternative algo-
rithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This aids in networks where large numbers of nodes
are present, and numerous nodes can be in collision. It
effectively accelerates the increase in the back-off time
in busy networks, and allows nodes not involved in the
collision to access the channel whilst the colliding
nodes await a reduction in channel activity. Once
channel activity is reduced, the nodes resolving the
collision time out their slot time counters as normal.
Manchester Encoder/Decoder (MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Layer Signaling) functions required
for a fully compliant ISO 8802-3 (IEEE/ANSI 802.3)
station. The MENDEC provides the encoding function
for data to be transmitted on the network using the high
accuracy on-board oscillator, driven by either the
crystal oscillator or an external CMOS level compatible
clock. The MENDEC also provides the decoding
function from data received from the network. The
MENDEC contains a Power On Reset (POR) circuit,
which ensures that all analog portions of the PCnet-32
controller are forced
into their correct state during power
up, and prevents
erroneous data transmission and/or
reception during this time.
External Crystal Characteristics
When using a crystal to drive the oscillator, the crystal
specification shown in Table 26 may be used to ensure
less than ±0.5 ns jitter at the transmit outputs.
Table 26. External Crystal Specification
*Requires trimming spec,: no trim is 50 ppm total.
External Clock Drive Characteristics
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than ±0.5 ns jitter at the transmit
outputs. See Table 27.
Parameter
Min
Nom
Max
Unit
1.Parallel Resonant
Frequency
20
MHz
2.Resonant Frequency Error
–
50
+50
PPM
3.Change in Resonant Frequency
With Respect To Temperature
(0
×
C
–
70
×
C)*
–
40
+40
PPM
20
50
pF
4.Crystal Load Capacitance
5.Motional Crystal
Capacitance (C1)
0.022
pF
6.Series Resistance
25
ohm
7.Shunt Capacitance
7
pF
8.Drive Level
TBD
mW
相關PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
發(fā)布緊急采購，3分鐘左右您將得到回復。