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參數(shù)資料
| 型號(hào)： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 167/228頁(yè) |
| 文件大小： | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
167
Table 51. EEDET Effects on EEPROM Operation
If EEN = 0 and no EEPROM read
function is currently active, then
EECS will be driven LOW. When
EEN = 0 and no EEPROM read
function is currently active, EESK
and EEDI pins will be driven by the
LED registers BCR5 and BCR4,
respectively. See Table 52.
EEN is set to ZERO by H_RESET
and is unaffected by S_RESET or
STOP.
3
EBUSY
EEPROM BUSY. This bit controls
the value of the SHFBUSY pin of the
PCnet-32 controller when the EEN
bit is set to ONE and the PREAD bit
is set to ZERO. This bit is used to
indicate to external EEPROM-
programmable logic that an
EEPROM access is occurring.
When user programming of the
EEPROM is desired through the
BCR19 EEPROM Port, then EBUSY
should be set to ONE before EEN is
set to ONE in systems where
EEPROM-programmable external
logic exists. At the end of the
EEPROM programming operation,
EBUSY should either remain set at
ONE until after EEN is set to ZERO,
or the user may reset EBUSY to
ZERO with EEN = 1 immediately
following a read of EEPROM byte
locations 35 and 36, which should
be the last accesses performed
during BCR19 accesses to the
EEPROM. A programmed PREAD
operation following the BCR19
EEPROM programming accesses
will cause the SHFBUSY pin to
become LOW if the EEPROM
checksum is verified.
EBUSY has no effect on the output
value of the SHFBUSY pin unless
the PREAD bit is set to ZERO and
the EEN bit is set to ONE.
EBUSY is set to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
2
ECS
EEPROM Chip Select. This bit is
used to control the value of the
EECS pin of the microwire interface
when the EEN bit is set to ONE and
the PREAD bit is set to ZERO. If
EEN =
“
1
”
and PREAD =
“
0
”
and
ECS is set to a ONE, then the EECS
pin will be forced to a HIGH level at
the rising edge of the next BCLK
following bit programming. If EEN =
“
1
”
and PREAD =
“
0
”
and ECS is set
to a ZERO, then the EECS pin will
be forced to a LOW level at the rising
edge of the next BCLK following bit
programming.
ECS has no effect on the output
value of the EECS pin unless the
PREAD bit is set to ZERO and the
EEN bit is set to ONE.
EEDET Value
(BCR19[3])
EEPROM
Connected
Result if PREAD is set to ONE
Result of Automatic EEPROM Read
Operation Following H_RESET
0
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is reset to ZERO.
First TWO EESK clock cycles
are generated, then EEPROM
read operation is aborted and
PVALID is reset to ZERO.
0
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
First TWO EESK clock cycles are
generated, then EEPROM read
operation is aborted and PVALID is
reset to ZERO.
1
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is reset to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result,
PVALID is reset to ZERO.
1
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass,
PVALID is set to ONE.
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