參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 146/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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146
Am79C965A
During H_RESET or S_RESET a
value of 16 is loaded in the BURST
register. If the DMAPLUS bit in
CSR4 is set, the DMA Cycle
Register is disabled. When the
ENTST bit in CSR4 is set, all writes
to this register will automatically
perform a decrement cycle.
When the Cycle Register times out
in the middle of a linear burst, the
linear burst will continue until a legal
starting address is reached, and
then the PCnet-32 controller will
relinquish the bus.
Therefore, if linear bursting is
enabled, and the user wishes the
PCnet-32 controller to limit bus
activity to desired_max transfers,
then the Cycle Register should be
programmed to a value of:
Burst count setting = (desired_ max
DIV (length of linear burst in
transfers) x length of linear burst in
transfers where DIV is the operation
that yields the INTEGER portion of
the
3
operation.
Note
:
If either Linear Burst Write is
enabled, the value has to be greater
than or equal to 4.
Read/write accessible only when
the STOP bit is set.
CSR82: Bus Activity Timer
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
DMABAT Bus Activity Timer Register. If the
TIMER bit in CSR4 is set, this
register contains the maximum
allowable time that PCnet-32
controller will take up on the system
bus during FIFO data transfers for a
single DMA cycle. The Bus Activity
Timer Register does not limit the
number of transfers during
Descriptor transfers.
The DMABAT value is interpreted as
an unsigned number with a
resolution of 0.1 μs. For instance, a
value of 51 μs would be
programmed with a value of 510. If
the TIMER bit in CSR4 is set,
DMABAT is enabled and must be
initialized by the user. The DMABAT
register is undefined until written.
When the ENTST bit in CSR4 is set,
all writes to this register will
automatically perform a decrement
cycle.
If the user has NOT enabled the
Linear Burst function and wishes the
PCnet-32 controller to limit bus
activity to MAX_TIME μs, then the
Burst Timer should be programmed
to a value of:
MAX_TIME- [(11 + 4w) x (BCLK
period)],
where w = wait states.
If the user has enabled the Linear
Burst function and wishes the
PCnet-32 controller to limit bus
activity to MAX_TIME μs, then the
Burst Timer should be programmed
to a value of:
MAX_TIME- [((3+lbs) x w + 10 + lbs)
x (BCLK period)],
where w = wait states and lbs =
linear burst size in number of
transfers per sequence.
This is because the PCnet-32
controller may use as much as one
“
linear burst size
”
plus three
transfers in order to complete the
linear burst before releasing the bus.
As an example, if the linear burst
size is four transfers, and the
number of wait states for the system
memory is two, and the BCLK period
is 30 ns and the MAX time allowed
on the bus is 3 μs, then the Burst
Timer should be programmed for:
MAX_TIME- [((3+lbs) x w + 10 +
lbs) x (BCLK period)], 3 mS - [(3 + 4)
x 2 +10 + 4) x (30 ns)] = 3 mS - (28
x 30 ns) = 3 - 0.84 mS = 2.16 mS.
Then, if the PCnet-32 controller
’
s
Bus ActivityTimer times out after
2.16 μs when the PCnet-32
controller has completed all but the
last three transfers of a linear burst,
the PCnet-32 controller may take as
much as 0.84 μs to complete the
bursts and release the bus. The bus
release will occur at 2.16 + 0.84 = 3
ms.
相關(guān)PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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