參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 114/228頁(yè)
文件大小： 1681K
代理商： AM79C965A
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Am79C965A
Table 38. Effect of EEDET on EEPROM Operation
Systems Without an EEPROM
Some systems may be able to save the cost of an
EEPROM by storing the ISO 8802-3 (IEEE/ANSI
802.3) station address and other configuration
information somewhere else in the system. For such a
system, a two step process is required. The first step
will get the PCnet-32 controller into its normal
operating mode within the system. The second step will
load the IEEE station address. The designer has
several choices:
1)
If the LED1 and SFBD functions are not needed in
the system
, then the system designer may connect the
EESK/LED1/SFBD pin to a resistive pull-down device.
This will indicate to the EEPROM auto-detection
function that no EEPROM is present, and the PCnet-32
controller will use Software Relocatable Mode to
acquire its I/O Base Address and other configuration
information (See the section on Software Relocatable
Mode).
2)
If either of the LED1 or SFBD functions is needed in
the system
, then the system designer will connect the
EESK/LED1/SFBD pin to a resistive pull-up device and
the EEPROM auto-detection function will incorrectly
conclude that an EEPROM is present in the system.
However, this will not pose a problem for the PCnet-32
controller, since it will recognize the lack of an
EEPROM at the end of the read operation, when the
checksum verification fails. At this point, the PCnet-32
controller into the Software Relocatable Mode to
acquire its I/O Base Address and other configuration
information (See the section on Software Relocatable
Mode).
In either case, following the execution of Software
Relocatable Mode, additional information, including the
ISO 8802-3 (IEEE/ANSI 802.3) station address, may
be loaded into the PCnet-32 controller. Note that the
IESRWE bit (bit 8 of BCR2) must be set before the
PCnet-32 controller will accept writes to the APROM
offsets within the PCnet-32 controller I/O resources
map. Startup code in the system BIOS can perform the
Software Relocatable Mode accesses, the IESRWE bit
write, and the APROM writes.
If compatibility to existing driver code is desired, then it
is not recommended that the ISO 8802-3 (IEEE/ANSI
802.3) station address be loaded into the Initialization
Block structure in memory instead of the APROM loca-
tions, since existing code typically expects to find the
ISO 8802-3 (IEEE/ANSI 802.3) station address at the
APROM offsets from the PCnet-32 controller I/O Base
Address.
Direct Access to the Microwire Interface
The user may directly access the microwire port
through the EEPROM register, BCR19. This register
contains bits that can be used to control the microwire
interface pins. By performing an appropriate sequence
of I/O accesses to BCR19, the user can effectively
write to and read from the EEPROM. This feature may
be used by a system configuration utility to program
hardware configuration information into the EEPROM.
EEDET Value
(BCR19[3])
EEPROM
Connected
Result if PREAD is set to ONE
Result of Automatic EEPROM Read
Operation Following H_RESET
0
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is reset to ZERO.
First TWO EESK clock cycles
are generated, then EEPROM
read operation is aborted and
PVALID is reset to ZERO.
0
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
First TWO EESK clock cycles are
generated, then EEPROM read
operation is aborted and PVALID is
reset to ZERO.
1
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is reset to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result,
PVALID is reset to ZERO.
1
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass,
PVALID is set to ONE.
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