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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 92/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
although the normal FCS computation and checking
will occur. Note that apart from pad stripping, the frame
will be passed unmodified to the host. If the length field
has a value of 46 or greater, the MAC engine will not
attempt to validate the length against the number of
bytes contained in the message.
If the frame terminates or suffers a collision before 64
bytes of information (after SFD) have been received,
the MAC engine will automatically delete the frame
from the Receive FIFO, without host intervention.
Addressing (Source and Destination Address
Handling)
The first 6 bytes of information after SFD will be inter-
preted as the destination address field. The MAC
engine provides facilities for physical, logical (multicast)
and broadcast address reception. In addition, multiple
physical addresses can be constructed (perfect
address filtering) using external logic in conjunction
with the EADI interface.
Error Detection (Physical Medium Transmission
Errors)
The MAC engine provides several facilities which
report and recover from errors on the medium. In
addition, the network is protected from gross errors due
to inability of the host to keep pace with the MAC
engine activity.
On completion of transmission, the following transmit
status is available in the appropriate TMD and CSR
areas:
I
The number of transmission retry attempts (ONE,
MORE or RTRY).
I
Whether the MAC engine had to Defer (DEF) due to
channel activity.
I
Excessive deferral (EXDEF), indicating that the
transmitter has experienced Excessive Deferral on
this transmit frame, where Excessive Deferral is de-
fined in ISO 8802-3 (IEEE/ANSI 802.3).
I
Loss of Carrier (LCAR) indicates that there was an
interruption in the ability of the MAC engine to mon-
itor its own transmission. Repeated LCAR errors in-
dicate a potentially faulty transceiver or network
connection.
I
Late Collision (LCOL) indicates that the transmis-
sion suffered a collision after the slot time. This is in-
dicative of a badly configured network. Late
collisions should not occur in a normal operating
network.
I
Collision Error (CER) indicates that the transceiver
did not respond with an SQE Test message within
the predetermined time after a transmission com-
pleted. This may be due to a failed transceiver, dis-
connected or faulty transceiver drop cable, or the
fact the transceiver does not support this feature (or
it is disabled).
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails
to keep the Transmit FIFO filled sufficiently, causing an
underflow, the MAC engine will guarantee the message
is either sent as a runt packet (which will be deleted by
the receiving station) or has an invalid FCS (which will
also cause the receiver to reject the message).
The status of each receive message is available in the
appropriate RMD and CSR areas. FCS and Framing
errors (FRAM) are reported, although the received
frame is still passed to the host. The error will only be
reported if an FCS error is detected and there are a non
integral number of bytes in the message. The MAC
engine will ignore up to 7 additional bits at the end of a
message (dribbling bits), which can occur under
normal network operating conditions. The reception of
8 additional bits will cause the MAC engine to de-
serialize the entire byte, and will result in the received
message and FCS being modified.
The PCnet-32 controller can handle up to 7 dribbling
bits when a received frame terminates. During the
reception, the FCS is generated on every serial bit
(including the dribbling bits) coming from the cable,
although the internally saved FCS value is only
updated on the eighth bit (on each byte boundary). The
framing error is reported to the user as follows:
I
If the number of dribbling bits are 1 to 7 and there is
no CRC (FCS) error, then there is no Framing error
(FRAM = 0).
I
If the number of dribbling bits are 1 to 7 and there is
a CRC (FCS) error, then there is also a Framing
error (FRAM = 1).
I
If the number of dribbling bits = 0, then there is no
Framing error. There may or may not be a CRC
(FCS) error.
Counters are provided to report the Receive Collision
Count and Runt Packet Count for network statistics and
utilization calculations.
Note that if the MAC engine detects a received frame
which has a 00b pattern in the preamble (after the first
8-bits which are ignored), the entire frame will be ig-
nored. The MAC engine will wait for the network to go
inactive before attempting to receive additional frames.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The 802.3/
Ethernet protocols define a media access mechanism
which permits all stations to access the channel with
equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter
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| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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