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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 79/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
79
address is reached, and then the PCnet-32 controller
will relinquish the bus. If the Bus Activity Timer Register
times out after the execution of the first T2 cycle of the
fourth from the last transfer cycle within a linear burst
DMA sequence, then the PCnet-32 controller will
complete the current linear burst sequence and will
execute a new linear burst sequence before releasing
the HOLD signal and relinquishing the bus. (Effectively,
the Bus Activity Timer time-out is treated in a manner
identical to the occurrence of a preemption event.)
Therefore, when programmed for Linear Burst mode,
the PCnet-32 controller bus mastership time may
exceed the Bus Activity Timer limit.
This is done because an immediate abort of the linear
burst due to timer expiration would leave the current
buffer pointer at an unaligned location. This would
cause an address alignment of several ordinary cycles
to be executed during the next FIFO DMA operation.
Repeated occurrences of this nature would
compromise the usefulness of the linear burst mode,
since this would increase the number of non-linear
burst cycles that are performed. This in turn would
increase the bus bandwidth requirement of the
PCnet-32 controller. Therefore, because the PCnet-32
controller Linear Burst operation does not strictly obey
the Burst Timer, the user should program the Burst
Timer value in such a manner as to include the
expected linear burst release time. If the user has
enabled the Linear Burst function, and wishes the
PCnet-32 controller to limit bus activity to MAX_TIME
ms, then the Burst Timer should be programmed to a
value of:
MAX_TIME- [((3+lbs) x w + 10 + lbs) x (BCLK period)]
This is because the PCnet-32 controller may use as
much as one
“
linear burst size
”
plus three transfers in
order to complete the linear burst before releasing the
bus.
As an example, if the linear burst size is 4 transfers, and
the number of wait states for the system memory is 2,
and the BCLK period is 30 ns and the MAX time
allowed on the bus is 3 ms, then the Burst Timer should
be programmed for:
MAX_TIME- [((3+lbs) x w + 10 + lbs)
x (BCLK period)];
3 ms
–
[(3 + 4) x 2 +10 + 4) x (30 ns)]
= 3 ms
–
(28 x 30 ns) = 3
–
0.84 ms = 2.16 ms.
Then, if the PCnet-32 controller
’
s Burst Timer times out
after 2.16 ms when the PCnet-32 controller has com-
pleted all but the last three transfers of a linear burst,
then the PCnet-32 controller
may
take as
much
as 0.84
ms to complete the bursts and release the bus. The bus
release will occur at 2.16 + 0.84 = 3 ms.
Burst Cycle Time Out During Linear Burst
When the Burst Cycle (CSR80 bits [7:0]) times out in
the middle of a linear burst, the linear burst will continue
until a legal starting address is reached, and then the
PCnet-32 controller will relinquish the bus.
The discussion for the Burst Cycle is identical to the
discussion for the Bus Activity Timer Register, except
that the quantities are in terms of transfers instead of in
terms of time.
The equation for the proper burst register setting is:
Burst count setting = (desired_max DIV (length of
linear burst in transfers)) x length of linear burst in
transfers, where DIV is the operation that yields
the INTEGER portion of the
3
operation.
Illegal Combinations of Watermark and LINBC
Certain combinations of watermark programming and
LINBC programming may create situations where no
linear bursting is possible, or where the FIFO may be
excessively read or excessively written. Such combina-
tions are declared as illegal.
Combinations of watermark settings and LINBC set-
tings must obey the following relationship:
watermark (in bytes)
LINBC (in bytes)
Combinations of watermark and LINBC settings that
violate this rule may cause unexpected behavior.
Slave Timing
Slave timing in the PCnet-32 controller is designed to
perform to both Am486 32-bit timing requirements and
VESA VL-Bus timing requirements at the same time.
Since the VESA VL-Bus is based upon Am486 bus tim-
ing, there is really little difference evident, except for
hold-off requirements on the part of the slave driving
the RDY, BRDY, and data signals when the high speed
write signal is false. VESA VL-Bus requires that none
of these signals are driven by the slave until the second
T2 cycle when the high speed write signal is false.
Since the PCnet-32 controller does not examine the
high-speed write bit, it assumes that this signal is never
true, and therefore always obeys the more stringent
requirement of not being allowed to drive RDY, BRDY
and the data bus until the second T2. In addition, the
PCnet-32 controller will drive RDY and BRDY inactive
for one half BCLK cycle at the end of the slave access,
immediately following the BCLK cycle in which the
PCnet-32 controller asserted RDY. Again, this behavior
is required by the VESA VL-Bus specification, but it is
not required for operation within an Am486 system.
The PCnet-32 controller performs in this manner,
regardless of the PCnet-32 controller mode setting.
Slave timing can generally be inferred from the bus
master timing diagrams, with the exception of the
following information:
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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