- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > Am79C965A (Advanced Micro Devices, Inc.) PCnet?-32 Single-Chip 32-Bit Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 62/228頁 |
| 文件大小： | 1681K |
| 代理商： | AM79C965A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當前第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁
62
Am79C965A
Transfers within a linear burst cycle will either be all
read or all write cycles, and will always be to
contiguous ascending addresses. Linear Bursting of
Read and Write operations can be individually enabled
or disabled through the BREADE and BWRITE bits of
BCR18 (bits 6 and 5).
Linear Burst DMA transfers should be considered as a
superset of the FIFO DMA transfers. Linear burst DMA
transfers will only be used for data transfers to and from
the PCnet-32 controller FIFOs and they will only be al-
lowed when the burst enable bits of BCR18 have been
set. Linear Read bursting and Linear Write bursting
have individual enable bits in BCR18. Any combination
of linear burst enable bit settings is permissible.
Linear bursting is not allowed in systems that have
BCLK frequencies above 33 MHz.
Linear bursting is
automatically disabled in VL-Bus systems that operate
above this frequency by connecting the VLBEN pin to
either ID(3) (for VL-Bus version 1.0 systems) or ID(4)
AND ID(3) AND ID(1) AND ID(0) (for VL-Bus version
1.1 or 2.0 systems). In Am486-style systems that have
BCLK frequencies above 33 MHz, disabling the linear
burst capability is ideally carried out through EEPROM
bit programming, since the EEPROM programming can
be setup for a particular machine
’
s architecture.
All byte lanes are always considered to be active during
all linear burst transfers. The BE3
–
BE0 signals will
reflect this fact.
Linear Burst DMA Starting Address Restrictions
A PCnet-32 controller linear burst will begin only when
the address of the current transfer meets the following
condition:
A[31:0] MOD (LINBC x 16) = 0,
The following table illustrates all possible starting ad-
dress values for all legal LINBC values. Note that
A[31:6] are don
’
t care values for all addresses. Also
note that while A[1:0] do not physically exist within a 32
bit system, they are valid bits within the buffer pointer
field of descriptor word 0. Thus, where A[1:0] are listed,
they refer to the lowest two bits of the descriptor
’
s buffer
pointer field. These bits will have an affect on determin-
ing when a PCnet-32 controller linear burst operation
may legally begin and they will affect the output values
of the BE3
–
BE0 pins, therefore they have been
included in Table 21 as A[1:0].
It is not necessary for the software to insure that the
buffer address pointer contained in descriptor word 0
matches the address restrictions given in the table.
If
the buffer pointer does not meet the conditions set forth
in the table, then the PCnet-32 controller will simply
postpone the start of linear bursting until enough
ordinary FIFO DMA transfers have been performed to
bring the current working buffer pointer value to a valid
linear burst starting address.
This operation is referred
to as
“
aligning
”
the buffer address to a valid linear burst
starting address. Once this has been done, the
PCnet-32 controller will recognize that the address for
the current access is a valid linear burst starting
address, and it will automatically begin to perform
linear burst accesses at that time, provided of course
that the software has enabled the linear burst mode.
Note that if the software
would
provide only valid linear
burst starting addresses in the buffer pointer, then the
PCnet-32 controller could avoid performing the align-
ment operation. It would begin linear burst accesses on
the very first of the buffer transfers thereby allowing a
slight gain in bus bandwidth efficiency.
Because of the linear burst starting address restrictions
given in the table above, the PCnet-32 controller linear
burst mode is completely compatible with the Am486-
style burst cycle when the LINBC[2:0] bits have been
programmed with the value of 001.
Table 21. Linear Burst Addess
LINBC[2:0]
LBS = Linear Burst
Size (No. of Transfers)
Linear Burst Addresses
Beginning A[5:0] =
(A[31:6] = Don
’
t Care)
0
0 (no linear bursting)
Not Applicable
1
4
00, 10, 20, 30
2
8
00, 20
4
16
00
3,5,6,7
Reserved
Not Applicable
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。