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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 128/228頁 |
| 文件大小： | 1681K |
| 代理商： | AM79C965A |
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128
Am79C965A
mastering addresses, as required
for a 32 bit address bus. Note that
the 16-bit software structures
specified by the SSIZE32 = 0 setting
will yield only 24 bits of address for
PCnet-32 controller bus master
accesses, while the 32-bit hard-
ware for which the PCnet-32
controller is intended will require 32
bits of address. Therefore,
whenever SSIZE32 = 0, the
IADR[31:24] bits will be appended to
the 24-bit initialization address, to
each 24-bit descriptor base address
and to each beginning 24-bit buffer
address in order to form complete
32-bit addresses. The upper 8 bits
that exist in the descriptor address
registers and the buffer address
registers which are stored on
board the
PCnet-32 controller will be
overwritten with the IADR[31:24]
value, so that CSR accesses to
these registers will show the 32 bit
address that includes the appended
field.
If SSIZE32 = 1, then software will
provide 32-bit pointer values for all
of the shared software structures
(i.e. descriptor bases and buffer
addresses), and therefore,
IADR[31:24] will not be written to the
upper 8 bits of any of these
resources, but it will be used as the
upper 8 bits of the initialization
address.
Read/Write accessible only when
the STOP bit in CSR0 is set.
Unaffected by H_RESET or
S_RESET or by setting the STOP
bit.
7-0 IADR[23:16] Bits 23 through 16 of the address of
the Initialization Block. Whenever
this register is written, CSR17 is
updated with CSR2
’
s contents.
Read/Write accessible only when
the STOP bit in CSR0 is set.
Unaffected by H_RESET or
S_RESET or by setting the STOP
bit.
CSR3: Interrupt Masks and Deferral Control
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
RES
Reserved location. Read and written
as zero.
14
BABLM
Babble Mask. If BABLM is set, the
BABL bit in CSR0 will be masked
and unable to set INTR flag in
CSR0.
Read/Write
BABLM is cleared by H_RESET or
S_RESET and is not affected by
STOP.
accessible
always.
13
RES
Reserved location. Read and written
as zero.
12
MISSM
Missed Frame Mask. If MISSM is
set, the MISS bit in CSR0 will be
masked and unable to set INTR flag
in CSR0.
Read/Write
MISSM is cleared by H_RESET or
S_RESET and is not affected by
STOP.
accessible
always.
11
MERRM Memory Error Mask. If MERRM is
set, the MERR bit in CSR0 will be
masked and unable to set INTR flag
in CSR0.
Read/Write
MERRM is cleared by H_RESET or
S_RESET and is not affected by
STOP.
accessible
always.
10
RINTM
Receive Interrupt Mask. If RINTM is
set, the RINT bit in CSR0 will be
masked and unable to set INTR flag
in CSR0.
Read/Write
RINTM is cleared by H_RESET or
S_RESET and is not affected by
STOP.
accessible
always.
9
TINTM
Transmit interrupt Mask. If TINTM is
set, the TINT bit in CSR0 will be
masked and unable to set INTR flag
in CSR0.
Read/Write
TINTM is cleared by H_RESET or
S_RESET and is not affected by
STOP.
accessible
always.
8
IDONM
Initialization Done Mask. If IDONM
is set, the IDON bit in CSR0 will be
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相關(guān)代理商/技術(shù)參數(shù) |
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